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Siehe Technische Spezifikationen

A1280A-1PG176M +BOM

Powerful FPGA with 8K system gates

Hersteller:

MICROSEMI CORP
Herstellerteil #:

A1280A-1PG176M
Datenblatt:

A1280A-1PG176M Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
ECCN Code:

3A001.A.2.C
HTS Code:

8542.39.00.01
Additional Feature:

MAX 140 I/OS
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an A1280A-1PG176M

A1280A-1PG176M Allgemeine Beschreibung

The A1280A-1PG176M is a highly versatile and efficient programmable logic device that offers 1280 logic elements in a convenient 176-pin PG176 package. With its reprogrammable functionality, this device provides unparalleled flexibility for implementing logic in a wide range of applications. Whether it's for industrial automation, consumer electronics, or telecommunications, the A1280A-1PG176M is designed to meet the diverse needs of modern technology

Hauptmerkmale

Highly Predictable Performance with 100% Automatic Placement and Routing
Device Sizes from 1,200 to 20,000 Gates
Up to 6 Fast, Low-Skew Clock Networks
Up to 202 User-Programmable I/O Pins
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
Proven Reliability Data Available
Successful Military/Avionics Supplier for Over 10 Years
ACT 3 Features
Highest-Performance, Highest-Capacity FPGA Family
System Performance to 60 MHz over Military Temperature
Low-Power 0.8µ CMOS Technology
3200DX Features
100 MHz System Logic Integration
Highest Speed FPGA SRAM, up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Low-Power 0.6µ CMOS Technology
1200XL Features
Pin for Pin Compatible with ACT 2
System Performance to 50 MHz over Military Temperature
Low-Power 0.6µ CMOS Technology
ACT 2 Features
Best-Value, High-Capacity FPGA Family
System Performance to 40 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology
ACT 1 Features
Lowest-Cost FPGA Family
System Performance to 20 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology

Spezifikationen

Part Life Cycle Code	Obsolete	Reach Compliance Code
ECCN Code	3A001.A.2.C	HTS Code	8542.39.00.01
Additional Feature	MAX 140 I/OS	Clock Frequency-Max	75 MHz
Combinatorial Delay of a CLB-Max	4.3 ns	JESD-30 Code	S-CPGA-P176
JESD-609 Code	e0	Length	39.878 mm
Moisture Sensitivity Level	3	Number of CLBs	1232
Number of Equivalent Gates	8000	Number of Inputs	140
Number of Logic Cells	1232	Number of Outputs	140
Number of Terminals	176	Operating Temperature-Max	125 °C
Operating Temperature-Min	-55 °C	Organization	1232 CLBS, 8000 GATES
Peak Reflow Temperature (Cel)	225	Power Supplies	5 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	7.874 mm	Supply Voltage-Max	5.5 V
Supply Voltage-Min	4.5 V	Supply Voltage-Nom	5 V
Surface Mount	NO	Technology	CMOS
Temperature Grade	MILITARY	Terminal Finish	TIN LEAD
Terminal Form	PIN/PEG	Terminal Pitch	2.54 mm
Terminal Position	PERPENDICULAR	Time@Peak Reflow Temperature-Max (s)	20
Width	39.878 mm

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