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Siehe Technische Spezifikationen

A3P060-TQG144 +BOM

536 CLBs, 60000 Gates, 350MHz, CMOS, PQFP144

Hersteller:

MICROCHIP TECHNOLOGY INC
Herstellerteil #:

A3P060-TQG144
Datenblatt:

A3P060-TQG144 Datenblatt (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Factory Lead Time:

52 Weeks
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an A3P060-TQG144

A3P060-TQG144 Allgemeine Beschreibung

The A3P060-TQG144 from Microchip Technology is a powerful FPGA with 60,000 System Gates, 2880 Logic Cells, and 72 I/Os. This makes it suitable for a wide range of customizable logic applications, providing ample flexibility for designing complex digital systems. With its 1 Mbit of embedded Flash memory, the need for external memory components is reduced, making it a cost-effective solution for configuration data storage. Operating at a maximum frequency of 250 MHz, the A3P060-TQG144 offers high-speed performance, making it ideal for demanding applications

Hauptmerkmale

High Capacity 15 k to 1 M System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/OsReprogrammable Flash Technology 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Instant On Level 0 Support Single-Chip Solution Retains Programmed Design when Powered OffHigh Performance 350 MHz System Performance 3.3 V, 66 MHz 64-Bit PCIIn-System Programming (ISP) and Security ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC3 devices) via JTAG (IEEE 1532compliant) FlashLock to Secure FPGA ContentsLow Power Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash SwitchesHigh-Performance Routing Hierarchy Segmented, Hierarchical Routing and Clock StructureAdvanced I/O 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V Bank-Selectable I/O Voltagesup to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os Programmable Output Slew Rate and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the ProASIC3 FamilyClock Conditioning Circuit (CCC) and PLL Six CCC Blocks, One with an Integrated PLL Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback Wide Input Frequency Range (1.5 MHz to 350 MHz)Embedded Memory 1 kbit of FlashROM User Nonvolatile Memory SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (1, 2, 4, 9, and 18 organizations) True Dual-Port SRAM (except 18)ARM Processor Support in ProASIC3 FPGAs M1 ProASIC3 DevicesARMCortex-M1 Soft Processor Available with or without Debug

Spezifikationen

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Factory Lead Time	52 Weeks
Clock Frequency-Max	350 MHz	JESD-30 Code	S-PQFP-G144
JESD-609 Code	e3	Length	20 mm
Moisture Sensitivity Level	3	Number of CLBs	1536
Number of Equivalent Gates	60000	Number of Terminals	144
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	1536 CLBS, 60000 GATES	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	1.6 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.425 V
Supply Voltage-Nom	1.5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	COMMERCIAL
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Width	20 mm

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