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Siehe Technische Spezifikationen

A3PE3000L-PQ208I +BOM

A3PE3000L-PQ208I - a high-performance FPGA ideal for various applications

Hersteller:

MICROSEMI CORP
Herstellerteil #:

A3PE3000L-PQ208I
Datenblatt:

A3PE3000L-PQ208I Datenblatt (PDF)
Part Life Cycle Code:

Transferred
HTS Code:

8542.39.00.01
JESD-30 Code:

S-PQFP-G208
JESD-609 Code:

e0
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an A3PE3000L-PQ208I

A3PE3000L-PQ208I Allgemeine Beschreibung

Crafted to cater to the evolving demands of modern technology, the A3PE3000L-PQ208I stands out as a reliable and efficient solution for a wide array of applications. Its robust design, coupled with advanced security features, makes it an ideal choice for industries where data protection is paramount. By combining performance, power efficiency, and security in a single package, the A3PE3000L-PQ208I sets a new standard for SoC FPGAs in the market

Hauptmerkmale

Military Temperature Tested and Qualified
Each Device Tested from –55°C to 125°C
Firm-Error Immune
Not Susceptible to Neutron-Induced Configuration Loss
Low Power
Dramatic Reduction in Dynamic and Static Power
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power†
Low Power Consumption in FlashFreeze Mode Allows for
Instantaneous Entry To / Exit From Low-Power FlashFreeze
Supports Single-Voltage System Operation
Low-Impedance Switches
High Capacity
600 k to 3 M System Gates
Up to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization

Spezifikationen

Part Life Cycle Code	Transferred	Reach Compliance Code
HTS Code	8542.39.00.01	JESD-30 Code	S-PQFP-G208
JESD-609 Code	e0	Length	28 mm
Moisture Sensitivity Level	3	Number of CLBs	75264
Number of Equivalent Gates	3000000	Number of Inputs	147
Number of Logic Cells	75264	Number of Outputs	147
Number of Terminals	208	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	Organization	75264 CLBS, 3000000 GATES
Peak Reflow Temperature (Cel)	225	Power Supplies	1.2/1.5,1.2/3.3 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	4.1 mm	Supply Voltage-Max	1.575 V
Supply Voltage-Min	1.14 V	Supply Voltage-Nom	1.2 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	INDUSTRIAL	Terminal Finish	TIN LEAD
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	20
Width	28 mm

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