Bezahlverfahren
ATF1508AS-10AU100 +BOM
The ATF1508AS-10AU100 CPLD boasts 128 macro cells and supports a wide voltage range of 4
TQFP-100-
Hersteller:
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Herstellerteil #:
ATF1508AS-10AU100
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Datenblatt:
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Maximum Operating Frequency:
125 MHz
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Number Of Macrocells:
128
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Number Of I/Os:
80 I/O
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Propagation Delay - Max:
10 ns
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EDA/CAD Modelle:
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ATF1508AS-10AU100 Allgemeine Beschreibung
From digital signal processing to communications and control systems, the ATF1508AS-10AU100 is a versatile solution for a multitude of applications. Its comprehensive set of features, including 512 registers and a single 3.3V power supply requirement, make it a reliable choice for engineers looking to implement complex functionality in their designs. Whether you're working on a cutting-edge research project or a commercial product, this FPGA offers the performance and flexibility needed to meet your requirements
Hauptmerkmale
- High-density, High-performance, Electrically-erasable Complex Programmable Logic Device
- – 128 Macrocells
- – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
- – 84, 100, 160 Pins
- – 7.5 ns Maximum Pin-to-pin Delay
- – Registered Operation up to 125 MHz
- – Enhanced Routing Resources
- Flexible Logic Macrocell
- – D/T/Latch Configured Flip-flops
- – Global and Individual Register Control Signals
- – Global and Individual Output Enable
- – Programmable Output Slew Rate
- – Programmable Output Open Collector Option
- – Maximum Logic Utilization by Burying a Register within a COM Output
- Advanced Power Management Features
- – Automatic 10 µA Standby for “L” Version
- – Pin-controlled 1 mA Standby Mode
- – Programmable Pin-keeper Inputs and I/Os
- – Reduced-power Feature per Macrocell
- Available in Commercial and Industrial Temperature Ranges
- Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages
- Advanced EE Technology
- – 100% Tested
- – Completely Reprogrammable
- – 10,000 Program/Erase Cycles
- – 20-year Data Retention
- – 2000V ESD Protection
- – 200 mA Latch-up Immunity
- JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
- Fast In-System Programmability (ISP) via JTAG
- PCI-compliant
- 3.3 or 5.0V I/O Pins
- Security Fuse Feature
- Green (Pb/Halide-free/RoHS Compliant) Package Options
- Enhanced Features
- Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
- Output Enable Product Terms
- Transparent-latch Mode
- Combinatorial Output with Registered Feedback within Any Macrocell
- Three Global Clock Pins
- ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
- Fast Registered Input from Product Term
- Programmable “Pin-keeper” Option
- VCC Power-up Reset Option
- Pull-up Option on JTAG Pins TMS and TDI
- Advanced Power Management Features
- – Edge-controlled Power-down “L”
- – Individual Macrocell Power Option
- – Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Spezifikationen
Product Category | EEPLD - Electronically Erasable Programmable Logic Devices | Maximum Operating Frequency | 125 MHz |
Number of Macrocells | 128 | Number of I/Os | 80 I/O |
Propagation Delay - Max | 10 ns | Operating Supply Voltage | 5 V |
Minimum Operating Temperature | - 40 C | Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT | Packaging | [ "Tray" ] |
Height | 0.9 mm | Length | 14 mm |
Moisture Sensitive | Yes | Product Type | EEPLD - Electronically Erasable Programmable Logic Devices |
Series | ATF1508AS | Factory Pack Quantity | 90 |
Subcategory | Programmable Logic ICs | Supply Voltage - Max | 5.5 V |
Supply Voltage - Min | 4.5 V | Width | 14 mm |
Unit Weight | 0.023175 oz |
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