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Siehe Technische Spezifikationen

CY37512P208-100NI +BOM

12ns response time on the 512-cell EE PLD with CMOS technology and PQFP208 package

Hersteller:

CYPRESS SEMICONDUCTOR CORP
Herstellerteil #:

CY37512P208-100NI
Datenblatt:

CY37512P208-100NI Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

208
Reach Compliance Code:

not_compliant
HTS Code:

8542.39.00.01
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an CY37512P208-100NI

CY37512P208-100NI Allgemeine Beschreibung

General DescriptionThe Ultra37000™ family of CMOSCPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM).

Hauptmerkmale

In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
3.3V and 5V versions
PCI-compatible[1]
Programmable bus-hold capabilities on all I/Os
Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering onan individual basis
— Product term sharing among local macrocells
Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
Consistent package/pinout offering across all densities
— Simplifies design migration
— Same pinout for 3.3V and 5.0V devices
Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages
— Lead(Pb)-free packages available

Spezifikationen

Part Life Cycle Code	Obsolete	Pin Count	208
Reach Compliance Code	not_compliant	HTS Code	8542.39.00.01
Additional Feature	512 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	Architecture	PLA-TYPE
Clock Frequency-Max	80 MHz	In-System Programmable	YES
JESD-30 Code	S-PQFP-G208	JESD-609 Code	e0
JTAG BST	YES	Length	28 mm
Moisture Sensitivity Level	3	Number of Dedicated Inputs	1
Number of I/O Lines	160	Number of Inputs	165
Number of Macro Cells	512	Number of Outputs	160
Number of Terminals	208	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	Organization	1 DEDICATED INPUTS, 160 I/O
Output Function	MACROCELL	Power Supplies	3.3/5 V
Programmable Logic Type	EE PLD	Propagation Delay	12 ns
Qualification Status	Not Qualified	Seated Height-Max	3.7 mm
Supply Voltage-Max	5.5 V	Supply Voltage-Min	4.5 V
Supply Voltage-Nom	5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	INDUSTRIAL
Terminal Finish	TIN LEAD	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Width	28 mm

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