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DS90C241 +BOM

5-MHz to 35-MHz DC-balanced 24-bit FPD-Link II serializer

Hersteller:

NS
Herstellerteil #:

DS90C241
Datenblatt:

DS90C241 Datenblatt (PDF)
Paket/Koffer:

TQFP-48
Produktart:

Line Driver or Receivers
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an DS90C241

DS90C241 Allgemeine Beschreibung

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.

Hauptmerkmale

5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
Individual Power-Down Controls for Both Transmitter and Receiver
Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
LOCK Output Flag to Ensure Data Integrity at Receiver Side
Balanced T_SETUP and T_HOLD Between RCLK and RDATA on Receiver Side
PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
All LVCMOS Inputs and Control Pins Have Internal Pulldown
On-Chip Filters for PLLs on Transmitter and Receiver
Temperature Range: –40°C to 105°C
Greater Than 8-kV HBM ESD Tolerant
Meets AEC-Q100 Compliance
Power Supply Range: 3.3 V ± 10%
48-Pin TQFP Package

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Verpackung

AVAQ bestimmt und verpackt alle Geräte auf der Grundlage der Schutzanforderungen gegen elektrostatische Entladung (ESD) und Feuchtigkeitsempfindlichkeit (MSL)..