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Siehe Technische Spezifikationen

EP1S20F484C7N +BOM

With 484 pins in a FC-FBGA package, the EP1S20F484C7N offers a robust and versatile solution for complex digital design projects

Hersteller:

Intel
Herstellerteil #:

EP1S20F484C7N
Datenblatt:

EP1S20F484C7N Datenblatt (PDF)
Series:

Stratix®
Programmabe:

Not Verified
Number Of LABs/CLBs:

1846
Number Of Logic Elements/Cells:

18460
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an EP1S20F484C7N

EP1S20F484C7N Allgemeine Beschreibung

In the realm of Field-Programmable Gate Arrays, the EP1S20F484C7N FPGA stands out as a member of the esteemed Stratix II family by Altera, now part of Intel. Boasting 20 thousand logic elements, this FPGA strikes a balance between computational power and versatility, making it suitable for a diverse array of applications. Its F484 package type ensures seamless compatibility with 484-pin FineLine BGA sockets, facilitating easy integration into electronic systems. The C7 speed grade guarantees optimal performance levels, catering to demanding computational requirements. Furthermore, the N temperature range signifies its ability to operate efficiently in commercial environments with temperatures ranging from 0°C to 85°C. To delve deeper into its technical nuances and capabilities, it is advisable to refer to the comprehensive datasheet

Hauptmerkmale

Configuration devices for SRAM-based LUT devices offer the following features:

Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices

Easy-to-use four-pin interface

Low current during configuration and near-zero standby mode current

Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers

Available in compact plastic packages

8-pin plastic dual in-line (PDIP) package

20-pin plastic J-lead chip carrier (PLCC) package

32-pin plastic thin quad flat pack (TQFP) package

EPC2 device has reprogrammable flash configuration memory

5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.

1149.1 JTAG interface

Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1

Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable

Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices

nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Spezifikationen

Series	Stratix®	Programmabe	Not Verified
Number of LABs/CLBs	1846	Number of Logic Elements/Cells	18460
Total RAM Bits	1669248	Number of I/O	361
Voltage - Supply	1.425V ~ 1.575V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)	Base Product Number	EP1S20

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