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Siehe Technische Spezifikationen

EP1S25F780I6N +BOM

EP1S25F780I6N - FPGA Stratix Family 25660 Cells at 450.05MHz with 130nm Technology and 1.5V, housed in a 780-Pin FC-FBGA package

Hersteller:

Intel
Herstellerteil #:

EP1S25F780I6N
Datenblatt:

EP1S25F780I6N Datenblatt (PDF)
Shipping Restrictions:

This product may require additional documentation to export from the United States.
Series:

Stratix EP1S25
Number Of Logic Elements:

25660 LE
Embedded Memory:

1.85 Mbit
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an EP1S25F780I6N

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

EP1S25F780I6N Allgemeine Beschreibung

The EP1S25F780I6N FPGA stands out as a key technology enabler in the realm of advanced digital design and embedded systems development. Featuring a generous pin count of 780, this component offers extensive capabilities for interfacing with external components, peripherals, and interfaces. The I6N speed grade and commercial temperature range ensure that the FPGA can deliver robust performance across a wide range of operating conditions, making it a versatile choice for diverse applications. With the EP1S25F780I6N, designers and engineers can unleash their creativity and innovation in crafting sophisticated electronic systems with exceptional flexibility and scalability

Hauptmerkmale

Configuration devices for SRAM-based LUT devices offer the following
features:
Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
Easy-to-use four-pin interface
Low current during configuration and near-zero standby mode current
Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
Available in compact plastic packages
8-pin plastic dual in-line (PDIP) package
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
EPC2 device has reprogrammable flash configuration memory
5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Spezifikationen

Product Category	FPGA - Field Programmable Gate Array	Shipping Restrictions	This product may require additional documentation to export from the United States.
Series	Stratix EP1S25	Number of Logic Elements	25660 LE
Adaptive Logic Modules - ALMs	-	Embedded Memory	1.85 Mbit
Number of I/Os	597 I/O	Supply Voltage - Min	1.5 V
Supply Voltage - Max	1.5 V	Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C	Mounting Style	SMD/SMT
Packaging	[ "Tray" ]	Maximum Operating Frequency	100 MHz
Moisture Sensitive	Yes	Number of Logic Array Blocks - LABs	2566 LAB
Operating Supply Current	90 mA	Operating Supply Voltage	1.5 V
Product Type	FPGA - Field Programmable Gate Array	Factory Pack Quantity	36
Subcategory	Programmable Logic ICs	Total Memory	1944576 bit
Tradename	Stratix	Part # Aliases	971728

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