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Siehe Technische Spezifikationen

EP1S30F780C6 +BOM

CMOS field-programmable gate array with 3819 configurable logic blocks and 32470 cells in a 29 x 29 mm PBGA780 package

Hersteller:

Intel
Herstellerteil #:

EP1S30F780C6
Datenblatt:

EP1S30F780C6 Datenblatt (PDF)
Series:

Stratix®
Programmabe:

Not Verified
Number Of LABs/CLBs:

3247
Number Of Logic Elements/Cells:

32470
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an EP1S30F780C6

EP1S30F780C6 Allgemeine Beschreibung

With its robust capabilities, compact form factor, and advanced features, the EP1S30F780C6 is a versatile and reliable choice for diverse applications. Its ability to deliver high-performance processing, support a variety of interfaces, and offer flexibility through advanced features makes it a valuable asset for industries seeking efficient and adaptable solutions

Hauptmerkmale

Configuration devices for SRAM-based LUT devices offer the following
features:
Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
Easy-to-use four-pin interface
Low current during configuration and near-zero standby mode current
Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
Available in compact plastic packages
8-pin plastic dual in-line (PDIP) package
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
EPC2 device has reprogrammable flash configuration memory
5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Spezifikationen

Series	Stratix®	Programmabe	Not Verified
Number of LABs/CLBs	3247	Number of Logic Elements/Cells	32470
Total RAM Bits	3317184	Number of I/O	597
Voltage - Supply	1.425V ~ 1.575V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)	Base Product Number	EP1S30

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