Bezahlverfahren
EP1S30F780C6N +BOM
The EP1S30F780C6N is a high-performance FPGA with a generous cell count, making it suitable for demanding applications."
780-BBGA,FCBGA-
Hersteller:
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Herstellerteil #:
EP1S30F780C6N
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Datenblatt:
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Series:
Stratix®
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Programmabe:
Not Verified
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Number Of LABs/CLBs:
3247
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Number Of Logic Elements/Cells:
32470
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EDA/CAD Modelle:
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Verfügbarkeit: 8712 Stck
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EP1S30F780C6N Allgemeine Beschreibung
The EP1S30F780C6N is a member of the Cyclone series of FPGAs, specifically designed for low-cost and low-power applications. With approximately 780 logic array blocks available for programming, this FPGA offers a balance between performance and energy efficiency. Its 0.6-micron process technology ensures that it delivers reliable and efficient performance while consuming minimal power. Additionally, being part of the first generation of the Cyclone family, this FPGA has proven its versatility and cost-effectiveness in various applications. Its standard plastic package makes it easy to integrate into different systems, offering flexibility and convenience to developers
Hauptmerkmale
- Configuration devices for SRAM-based LUT devices offer the following
- features:
- Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
- Easy-to-use four-pin interface
- Low current during configuration and near-zero standby mode current
- Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
- Available in compact plastic packages
- 8-pin plastic dual in-line (PDIP) package
- 20-pin plastic J-lead chip carrier (PLCC) package
- 32-pin plastic thin quad flat pack (TQFP) package
- EPC2 device has reprogrammable flash configuration memory
- 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
- 1149.1 JTAG interface
- Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
- Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
- Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
- nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
Spezifikationen
Series | Stratix® | Programmabe | Not Verified |
Number of LABs/CLBs | 3247 | Number of Logic Elements/Cells | 32470 |
Total RAM Bits | 3317184 | Number of I/O | 597 |
Voltage - Supply | 1.425V ~ 1.575V | Mounting Type | Surface Mount |
Operating Temperature | 0°C ~ 85°C (TJ) | Base Product Number | EP1S30 |
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In Stock: 8.712
Minimum Order: 1
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