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EP20K200EFC484-2X +BOM

EP20K200EFC484-2X is a Field Programmable Gate Array CPLD with 832 Macro and 376 IOs

Hersteller:

Intel
Herstellerteil #:

EP20K200EFC484-2X
Datenblatt:

EP20K200EFC484-2X Datenblatt (PDF)
Series:

APEX 20K EP20K200E
Number Of Logic Elements:

8320 LE
Embedded Memory:

104 kbit
Number Of I/Os:

376 I/O
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an EP20K200EFC484-2X

EP20K200EFC484-2X Allgemeine Beschreibung

The EP20K200EFC484-2X is a cutting-edge Field-Programmable Gate Array (FPGA) from Altera's renowned Stratix family. With a staggering 200,000 logic elements and 6,500 Kbits of embedded memory, this FPGA is a powerhouse of performance and versatility. Its 484-pin FineLine BGA package with a 1.0mm ball pitch ensures a compact yet robust form factor, making it ideal for a wide array of applications across various industries

Hauptmerkmale

Configuration devices for SRAM-based LUT devices offer the following
features:
Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
Easy-to-use four-pin interface
Low current during configuration and near-zero standby mode current
Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
Available in compact plastic packages
8-pin plastic dual in-line (PDIP) package
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
EPC2 device has reprogrammable flash configuration memory
5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Spezifikationen

Product Category	FPGA - Field Programmable Gate Array	Series	APEX 20K EP20K200E
Number of Logic Elements	8320 LE	Adaptive Logic Modules - ALMs	-
Embedded Memory	104 kbit	Number of I/Os	376 I/O
Supply Voltage - Min	2.5 V	Supply Voltage - Max	2.5 V
Minimum Operating Temperature	0 C	Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT	Packaging	[ "Tray" ]
Maximum Operating Frequency	170 MHz	Moisture Sensitive	Yes
Number of Gates	526000	Number of Logic Array Blocks - LABs	832 LAB
Operating Supply Voltage	2.5 V	Product Type	FPGA - Field Programmable Gate Array
Factory Pack Quantity	60	Subcategory	Programmable Logic ICs
Total Memory	106496 bit	Tradename	APEX 20K
Part # Aliases	966782

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