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Siehe Technische Spezifikationen

GAL16V8D-15LJ +BOM

20-Pin PLCC package for easy integration

Hersteller:

LATTICE SEMICONDUCTOR CORP
Herstellerteil #:

GAL16V8D-15LJ
Datenblatt:

GAL16V8D-15LJ Datenblatt (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

20
Reach Compliance Code:

not_compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an GAL16V8D-15LJ

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

GAL16V8D-15LJ Allgemeine Beschreibung

The GAL16V8D-15LJ is a versatile and efficient complex programmable logic device (CPLD) designed for medium-scale digital design applications. With its 16 macrocells and a speed grade of 15ns, this CPLD offers high-speed operation and low power consumption, making it an ideal choice for various digital circuit implementations. It belongs to the GAL16V8 family of GAL devices manufactured by Lattice Semiconductor Corporation, known for their advanced CMOS technology

Hauptmerkmale

HIGH PERFORMANCE E2CMOS®TECHNOLOGY
—3.5 ns Maximum Propagation Delay
—Fmax = 250 MHz
—3.0 ns Maximum from Clock Input to Data Output
—UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
—75mA Typ Icc on Low Power Device
—45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E2CELL TECHNOLOGY
—Reconfigurable Logic
—Reprogrammable Cells
—100% Tested/100% Yields
—High Speed Electrical Erasure (<100ms)
—20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
—Maximum Flexibility for Complex Logic Designs
—Programmable Output Polarity
—Also Emulates 20-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
—100% Functional Testability
APPLICATIONS INCLUDE:
—DMA Control
—State Machine Control
—High Speed Graphics Processing
—Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION

LATTICE SEMICONDUCTOR CORP Originalbestand

Spezifikationen

Pbfree Code	No	Part Life Cycle Code	Obsolete
Pin Count	20	Reach Compliance Code	not_compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Architecture	PAL-TYPE	Clock Frequency-Max	45.5 MHz
JESD-30 Code	S-PQCC-J20	JESD-609 Code	e0
Length	8.9662 mm	Moisture Sensitivity Level	1
Number of Dedicated Inputs	8	Number of I/O Lines	8
Number of Inputs	18	Number of Outputs	8
Number of Product Terms	64	Number of Terminals	20
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	8 DEDICATED INPUTS, 8 I/O	Output Function	MACROCELL
Peak Reflow Temperature (Cel)	225	Power Supplies	5 V
Programmable Logic Type	EE PLD	Propagation Delay	15 ns
Qualification Status	Not Qualified	Seated Height-Max	4.572 mm
Supply Voltage-Max	5.25 V	Supply Voltage-Min	4.75 V
Supply Voltage-Nom	5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	COMMERCIAL
Terminal Finish	Tin/Lead (Sn85Pb15)	Terminal Form	J BEND
Terminal Pitch	1.27 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	8.9662 mm

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