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ISPPAC-CLK5610AV-01TN48I +BOM

Lead Free Technology

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

ISPPAC-CLK5610AV-01TN48I
Datenblatt:

ISPPAC-CLK5610AV-01TN48I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Obsolete
Pin Count:

48
Reach Compliance Code:

compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an ISPPAC-CLK5610AV-01TN48I

ISPPAC-CLK5610AV-01TN48I Allgemeine Beschreibung

In addition to its exceptional performance metrics, this IC also comes equipped with programmable features like output dividers and delay control, empowering designers to tailor clock outputs to precise system requirements. The ISPPAC-CLK5610AV-01TN48I operates efficiently on a low power supply voltage, paving the way for energy-efficient solutions in power-sensitive applications. Its compact form factor and high level of integration facilitate seamless integration across a range of electronic devices, making it an ideal choice for networking equipment, communication systems, and industrial automation applications

Hauptmerkmale

Four Operating Configurations
Zero delay buffer
Zero delay and non-zero delay buffer
Dual non-zero delay buffer
Non-zero delay buffer with output divider
8MHz to 267MHz Input/Output Operation
Low Output to Output Skew (<100ps)
Low Jitter Peak-to-Peak (<70 ps)
Up to 20 Programmable Fan-out Buffers
Programmable single-ended output standards and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Programmable output impedance
- 40 to 70Ω in 5Ω increments
Programmable slew rate
Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
Programmable lock detect
Three “Power of 2” output dividers (5-bit)
Programmable on-chip loop filter
Compatible with spread spectrum clocks
Internal/external feedback
Precision Programmable Phase Adjustment (Skew) Per Output
8 settings; minimum step size 156ps
- Locked to VCO frequency
Up to +/- 5ns skew range
Coarse and fine adjustment modes
Up to Three Clock Frequency Domains
Flexible Clock Reference and External Feedback Inputs
Programmable single-ended or differential input reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL
Clock A/B selection multiplexer
Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
Programmable termination
All Inputs and Outputs are Hot Socket Compliant
Full JTAG Boundary Scan Test In-System Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
48-pin and 64-pin TQFP Packages

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Obsolete
Pin Count	48	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Family	5600
Input Conditioning	DIFFERENTIAL	JESD-30 Code	S-PQFP-G48
JESD-609 Code	e3	Length	7 mm
Logic IC Type	PLL BASED CLOCK DRIVER	Moisture Sensitivity Level	3
Number of Functions	1	Number of Inverted Outputs
Number of Terminals	48	Number of True Outputs	10
Operating Temperature-Max	85 °C	Operating Temperature-Min	-40 °C
Output Characteristics	3-STATE	Peak Reflow Temperature (Cel)	260
Propagation Delay (tpd)	8.8 ns	Qualification Status	Not Qualified
Same Edge Skew-Max (tskwd)	0.05 ns	Seated Height-Max	1.6 mm
Supply Voltage-Max (Vsup)	3.6 V	Supply Voltage-Min (Vsup)	3 V
Supply Voltage-Nom (Vsup)	3.3 V	Surface Mount	YES
Temperature Grade	INDUSTRIAL	Terminal Finish	MATTE TIN
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Width	7 mm
fmax-Min	400 MHz	Series	ispClock™
Programmabe	Verified	PLL	Yes with Bypass
Input	HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL	Output	EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
Number of Circuits	1	Ratio - Input:Output	1:10
Differential - Input:Output	Yes/Yes	Frequency - Max	400MHz
Divider/Multiplier	Yes/No	Voltage - Supply	3V ~ 3.6V
Operating Temperature	-40°C ~ 85°C	Mounting Type	Surface Mount
Base Product Number	ISPPAC-CLK5610A

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