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LFXP2-8E-5FTN256I +BOM

LFXP2-8E-5FTN256I is an FPGA with 8K LUTs

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LFXP2-8E-5FTN256I
Datenblatt:

LFXP2-8E-5FTN256I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

256
Reach Compliance Code:

compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LFXP2-8E-5FTN256I

LFXP2-8E-5FTN256I Allgemeine Beschreibung

Meet the Lattice Semiconductor LFXP2-8E-5FTN256I FPGA, a powerhouse of performance and efficiency. Featuring an impressive array of 2,016 LUTs, 9,216 flip-flops, and 18 multipliers, this FPGA is tailor-made for demanding applications that require both speed and energy conservation. Its compact 256-pin FBGA package is perfect for space-constrained designs, while the 1.2V core voltage ensures low power consumption. With built-in block RAM, PLLs for clock management, and SERDES capabilities for high-speed data transfer, this FPGA covers all the bases for advanced applications. Its support for various I/O standards adds further flexibility and compatibility, making the LFXP2-8E-5FTN256I a standout choice in the world of field-programmable gate arrays

Hauptmerkmale

Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Supports up to eight PowerPC bus masters with unlimited slave device support.
Supports two outstanding bus accesses.
Supports address only transfer and address bus retry.
Independent address bus and data bus tenure with separate bus grant and data bus grant.
Option for fixed priority assignment or rotating priority scheme.
Designed for ASIC or programmable logic device implementations in various system environments.
Fully static design with edge triggered flip-flops.
Optimized for ispXPGA product family.

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	256	Reach Compliance Code	compliant
ECCN Code	3A991.D	HTS Code	8542.39.00.01
Clock Frequency-Max	435 MHz	Combinatorial Delay of a CLB-Max	0.494 ns
JESD-30 Code	S-PBGA-B256	JESD-609 Code	e1
Length	17 mm	Moisture Sensitivity Level	3
Number of CLBs	1000	Number of Inputs	201
Number of Logic Cells	8000	Number of Outputs	201
Number of Terminals	256	Operating Temperature-Max	100 °C
Operating Temperature-Min	-40 °C	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	2.1 mm	Supply Voltage-Max	1.26 V
Supply Voltage-Min	1.14 V	Supply Voltage-Nom	1.2 V
Surface Mount	YES	Technology	CMOS
Terminal Finish	TIN SILVER COPPER	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Width	17 mm

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