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Siehe Technische Spezifikationen

MT29F8G08ABBCAH4:C +BOM

63-Pin VFBGA - Small form factor for space-constrained applications

Hersteller:

Micron Technology Inc.
Herstellerteil #:

MT29F8G08ABBCAH4:C
Datenblatt:

MT29F8G08ABBCAH4:C Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.32.00.51
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an MT29F8G08ABBCAH4:C

MT29F8G08ABBCAH4:C Allgemeine Beschreibung

Micron Technology's MT29F8G08ABBCAH4:C is a game-changing NAND flash memory chip that offers unparalleled performance and reliability. With a capacity of 8 gigabits and high-speed data transfer rates, this chip is designed to meet the demands of data-intensive applications in various electronic devices such as smartphones, tablets, and solid-state drives. Operating at a voltage range of 2.7V to 3.6V, it is compatible with a wide range of systems, providing flexibility and versatility. Its multi-level cell (MLC) design strikes the perfect balance between cost and performance, making it a cost-effective and efficient storage solution. Additionally, the chip incorporates advanced error correction techniques to ensure data integrity and reliability, essential for seamless operation in today's digital landscape

Hauptmerkmale

Open NAND Flash Interface (ONFI) 1.0-compliant1
Single-level cell (SLC) technology
Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks 16Gb: 16,384 blocks
Asynchronous I/O performance
– tRC/tWC: 20ns (3.3V), 25ns (1.8V)
Array performance
– Read page: 25µs 3
– Program page: 200µs (TYP: 1.8V, 3.3V)3
– Erase block: 700µs (TYP)
Command set: ONFI NAND Flash Protocol
Advanced command set
– Program page cache mode4
– Read page cache mode 4
– One-time programmable (OTP) mode
– Two-plane commands 4
– Interleaved die (LUN) operations
– Read unique ID
– Block lock (1.8V only)
– Internal data move
Operation status byte provides software method for detecting
– Operation completion
– Pass/fail condition
– Write-protect status
Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion
WP# signal: Write protect entire device
First block (block address 00h) is valid when ship ped from factory with ECC. For minimum required ECC, see Error Management.
Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000
RESET (FFh) required as first command after power-on
Alternate method of device initialization (Nand_In it) after power up (contact factory)
Internal data move operations supported within the plane from which data is read
Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
Operating voltage range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
Package
– 48-pin TSOP type 1, CPL2
– 63-ball VFBGA

Spezifikationen

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.32.00.51
Access Time-Max	30 ns	Command User Interface	YES
Data Polling	NO	JESD-30 Code	R-PBGA-B63
Memory Density	8589934592 bit	Memory IC Type	FLASH
Memory Width	8	Number of Sectors/Size	4K
Number of Terminals	63	Number of Words	1073741824 words
Number of Words Code	1000000000	Operating Temperature-Max	70 °C
Operating Temperature-Min		Organization	1GX8
Page Size	4K words	Parallel/Serial	PARALLEL
Programming Voltage	1.8 V	Qualification Status	Not Qualified
Ready/Busy	YES	Sector Size	256K
Standby Current-Max	0.00005 A	Supply Current-Max	0.02 mA
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	COMMERCIAL
Terminal Form	BALL	Terminal Pitch	0.8 mm
Terminal Position	BOTTOM	Toggle Bit	NO
Type	SLC NAND TYPE

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