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Siehe Technische Spezifikationen

PVI-2003A +BOM

Timing Controller IC

Hersteller:

PVI
Herstellerteil #:

PVI-2003A
Datenblatt:

PVI-2003A Datenblatt (PDF)
HTSUSA:

8542390001
Schedule B:

8542390000
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an PVI-2003A

Hauptmerkmale

Single cycle 8051 CPU core
DC to 67 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, multiple security features
Up to 8 KB Flash ECC or configuration storage
Up to 8 KB SRAM memory
Up to 2 KB EEPROM memory, 1M cycles, 20 years retention
24 channel DMA with multilayer AHB bus access
Programmable chained descriptors and priorities
High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5V to 5.5V
High efficiency boost regulator from 0.5V input to 1.8V-5.0V output
330 µA at 1 MHz, 1.2 mA at 6 MHz, 5.6 mA at 40 MHz
Low power modes including:
200 nA hibernate mode with RAM retention and LVD
1 µA sleep mode with real time clock and low voltage reset
Versatile I/O system
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1])
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments[1]
1.2V to 5.5V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt trigger TTL inputs
All GPIO configurable as open drain high/low, pull up/down, High-Z, or strong output
Configurable GPIO pin state at power on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable PLD based Universal Digital Blocks
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[1]
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
8, 16, 24, and 32-bit timers, counters, and PWMs
SPI, UART, I2C
Many others available in catalog
Library of advanced peripherals
Cyclic Redundancy Check (CRC)
Pseudo Random Sequence (PRS) generator
LIN Bus 2.0
Quadrature decoder
Analog peripherals (1.71V ≤ Vdda ≤ 5.5V)
1.024V±0.9% internal voltage reference across -40°C to +85°C (14 ppm/°C)
Configurable Delta-Sigma ADC with 12-bit resolution
Programmable gain stage: x0.25 to x16
12-bit mode, 192 ksps, 70 dB SNR, 1 bit INL/DNL
67 MHz, 24-bit fixed point digital filter block (DFB) to implement FIR and IIR filters[1]
Up to four 8-bit, 8 Msps IDACs or 1 Msps VDACs
Four comparators with 75 ns response time
Up to four uncommitted opamps with 25 mA drive capability
Up to four configurable multifunction analog blocks. Example configurations are PGA, TIA, Mixer, and Sample and Hold
Programming, debug, and trace
JTAG (4 wire), Serial Wire Debug (SWD) (2 wire), and Single Wire Viewer (SWV) interfaces
8 address and 1 data breakpoint
4 KB instruction trace buffer
Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces
Precision, programmable clocking
1 to 66 MHz internal ±1% oscillator (over full temperature and voltage range) with PLL
4 to 33 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 67 MHz
32.768 kHz watch crystal oscillator
Low power internal oscillator at 1 kHz, 100 kHz
Temperature and packaging
-40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options

Spezifikationen

HTSUSA

8542390001

Schedule B

8542390000

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