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Siehe Technische Spezifikationen

SI53307-B-GMR +BOM

Designed for precise timing applications in electronic devices

Hersteller:

SILICON
Herstellerteil #:

SI53307-B-GMR
Datenblatt:

SI53307-B-GMR Datenblatt (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
Additional Feature:

ALSO OPERATES AT 2.5 V AND 3.3 V SUPPLY
Family:

53307
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an SI53307-B-GMR

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

SI53307-B-GMR Allgemeine Beschreibung

The SI53307-B-GMR is a versatile and highly integrated clock generator and jitter attenuator designed for various applications in telecommunications, networking, and industrial systems. With its wide range of features, including multiple clock outputs configurable up to 700 MHz, advanced jitter attenuation techniques, and support for various output formats, this device offers flexibility and high performance in system design. The integrated EEPROM makes customization and configuration of device settings effortless, while its wide supply voltage range and temperature range enhance its versatility and reliability in demanding environments. Additionally, the SI53307-B-GMR's compact package and low power consumption make it well-suited for space-constrained and power-sensitive applications

Hauptmerkmale

Supports single-ended or differential input clock signals
Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs
Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
Wide frequency range
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator allows system clock monitoring
Output Enable (OEB) pin allows glitchless control of output clocks
Low power: 10 mA typical core current
Industrial temperature range: –40 to +85 °C
Small size: 24-lead, 4 x 4 mm QFN

Spezifikationen

Part Life Cycle Code	Active	Reach Compliance Code	compliant
Additional Feature	ALSO OPERATES AT 2.5 V AND 3.3 V SUPPLY	Family	53307
Input Conditioning	DIFFERENTIAL	JESD-30 Code	S-XQCC-N16
Length	3 mm	Logic IC Type	LOW SKEW CLOCK DRIVER
Number of Functions	2	Number of Inverted Outputs
Number of Terminals	16	Number of True Outputs	6
Operating Temperature-Max	85 °C	Operating Temperature-Min	-40 °C
Packing Method	TR	Power Supply Current-Max (ICC)	100 mA
Prop. Delay@Nom-Sup	1.075 ns	Propagation Delay (tpd)	1.075 ns
Same Edge Skew-Max (tskwd)	0.12 ns	Seated Height-Max	0.9 mm
Supply Voltage-Max (Vsup)	1.89 V	Supply Voltage-Min (Vsup)	1.71 V
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Terminal Form	NO LEAD	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Width	3 mm

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