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Siehe Technische Spezifikationen

SM32C6713BGDPM30EP +BOM

Enhanced product C6713 floating-point DSP

Hersteller:

TEXAS INSTRUMENTS INC
Herstellerteil #:

SM32C6713BGDPM30EP
Datenblatt:

SM32C6713BGDPM30EP Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

272
Reach Compliance Code:

not_compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an SM32C6713BGDPM30EP

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

SM32C6713BGDPM30EP Allgemeine Beschreibung

Equipped with an integrated memory controller that supports external SDRAM and SRAM, the SM32C6713BGDPM30EP offers ample storage for data processing. Its array of peripherals, including UARTs, I2C interfaces, and timers, allows for seamless integration with other components in a system

Hauptmerkmale

Highest Performance Floating Point Digital Signal Processors (DSPs): C6713/C6713B
- Eight 32 Bit Instructions/Cycle
- 32/64 Bit Data Word
- 200 and 300 MHz Clock Rate
- 5 Instruction Cycle Times
- 2400/1800 and 1600/1200 MIPS/MFLOPS
- Rich Peripheral Set, Optimized for Audio
- Highly Optimized C/C++ Compiler
Advanced Very Long Instruction Word (VLIW) 320C67x DSP Core
- Eight Independent Functional Units:
  - Two ALUs (Fixed Point)
  - Four ALUs (Floating Point and Fixed Point)
  - Two Multipliers (Floating Point and Fixed Point)
- Load Store Architecture With 32 32-Bit General Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Native Instructions for IEEE 754
- Byte Addressable (8/16/32 Bit Data)
- 8 Bit Overflow Protection
- Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
L1/L2 Memory Architecture
- 4K Byte L1P Program Cache (Direct-Mapped)
- 4K Byte L1D Data Cache (2-Way)
- 256K Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM,
  and 192K Byte Additional L2 Mapped RAM
Device Configuration
- Boot Mode: HPI, 8/16/32 Bit ROM Boot
- Endianness: Little Endian, Big Endian
32 Bit External Memory Interface (EMIF)
- Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
- 512M Byte Total Addressable External Memory Space
Enhanced Direct Memory Access (EDMA) Controller (16 Independent Channels)
16 Bit Host Port Interface (HPI)
Two Multichannel Audio Serial Ports (McASPs)
- Two Independent Clock Zones Each (One TX and One RX)
- Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
- Wide Variety of I²S™ and Similar Bit Stream Formats
- Integrated Digital Audio Interface Transmitter (DIT)
- Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I²C™ Bus)
Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
- Serial Peripheral Interface (SPI)
- High Speed TDM Interface
- AC97 Interface
Two 32 Bit General Purpose Timers
Dedicated GPIO Module With 16 Pins (External Interrupt Capable)
Flexible Phase Locked Loop (PLL) Based Clock Generator Module
IEEE-1149.1 (JTAG) ⁽¹⁾ Boundary-Scan Compatible
272 Ball, Ball Grid Array Package (GDP)
0.13 µm/6 Level Copper Metal Process
- CMOS Technology
3.3 V I/Os, 1.26 V Internal
SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Military (–55°C/125°C) Temperature Range⁽²⁾
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability

⁽¹⁾ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
⁽²⁾ Custom temperature ranges available
2320C67x, TMS320C6000, TMS320C67x, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x are trademarks of Texas Instruments.

Spezifikationen

Source Content uid	SM32C6713BGDPM30EP	Pbfree Code	Yes
Part Life Cycle Code	Active	Pin Count	272
Reach Compliance Code	not_compliant	ECCN Code	3A001.A.2.C
HTS Code	8542.31.00.01	Additional Feature	ALSO REQUIRES 3.3V SUPPLY
Address Bus Width	22	Barrel Shifter	NO
Bit Size	32	Boundary Scan	YES
Clock Frequency-Max	250 MHz	External Data Bus Width	32
Format	FLOATING POINT	Integrated Cache	YES
Internal Bus Architecture	MULTIPLE	JESD-30 Code	S-PBGA-B272
JESD-609 Code	e0	Length	27 mm
Low Power Mode	YES	Moisture Sensitivity Level	3
Number of DMA Channels	16	Number of External Interrupts	4
Number of Terminals	272	Number of Timers	2
Operating Temperature-Max	125 °C	Operating Temperature-Min	-55 °C
Peak Reflow Temperature (Cel)	220	Power Supplies	1.2,3.3 V
Qualification Status	Not Qualified	Seated Height-Max	2.57 mm
Supply Voltage-Max	1.32 V	Supply Voltage-Min	1.2 V
Supply Voltage-Nom	1.26 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	MILITARY
Terminal Finish	Tin/Lead (Sn/Pb)	Terminal Form	BALL
Terminal Pitch	1.27 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	27 mm
uPs/uCs/Peripheral ICs Type	DIGITAL SIGNAL PROCESSOR, OTHER

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