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Siehe Technische Spezifikationen

TJA1021T,112 +BOM

LIN Transceiver with Integrated Vreg 20kBd Automotive 8-Pin SO Bulk

Hersteller:

NXP Semiconductor
Herstellerteil #:

TJA1021T,112
Datenblatt:

TJA1021T,112 Datenblatt (PDF)
Feature-pin-count:

8
Feature-cecc-qualified:

No
Feature-esd-protection:

Yes
Feature-military:

No
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an TJA1021T,112

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

TJA1021T,112 Allgemeine Beschreibung

The TJA1021 is the interface between the Local Interconnect Network (LIN) leader/follower protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.1/SAE J2602 compliant. The TJA1021 is pin-to-pin compatible with the TJA1020 with an improved ElectroStatic Discharge (ESD) specification.The transmit data stream of the protocol controller at the transmit data input (TXD) is converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a leader application, an external resistor in series with a diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller.In Sleep mode, the power consumption of the TJA1021 is very low. In failure modes, the power consumption is reduced to a minimum.

Hauptmerkmale

General
LIN 2.1/SAE J2602 compliant
Baud rate up to 20 kBd
Very low ElectroMagnetic Emission (EME)
High ElectroMagnetic Immunity (EMI)
Passive behavior in unpowered state
Input levels compatible with 3.3 V and 5 V devices
Integrated termination resistor for LIN follower applications
Wake-up source recognition (local or remote)
K-line compatible
Pin-to-pin compatible with TJA1020
Available in SO8 and HVSON8 packages
Leadless HVSON8 package (3.0 mm × 3.0 mm) with improved Automated Optical Inspection (AOI) capability
Low Power Management
Very low current consumption in Sleep mode with local and remote wake-up
Protection Mechanisms
High ESD robustness: ±6 kV according to IEC 61000-4-2 for pins LIN, VBAT and WAKE_N
Transmit data (TXD) dominant time-out function
Bus terminal and battery pin protected against transients in the automotive environment (ISO 7637)
Bus terminal short-circuit proof to battery and ground
Thermally protected

Anwendung

Automotive

Spezifikationen

feature-maximum-operating-supply-voltage-v		feature-process-technology
feature-packaging		feature-minimum-operating-supply-voltage-v
feature-rad-hard		feature-pin-count	8
feature-cecc-qualified	No	feature-esd-protection	Yes
feature-military	No	feature-aec-qualified	Yes
feature-aec-qualified-number	AEC-Q100	feature-auto-motive	Yes
feature-p-pap	Yes	feature-eccn-code	EAR99
feature-svhc		feature-svhc-exceeds-threshold	No

Image Thumbnail - TJA1021 Top Isometric View

Servicerichtlinien und andere

After-Sales- und Abwicklungsbezogen

Zahlung

Bezahlverfahren

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Geldgramm

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[email protected]

Versand & Verpackung

Versandart

Fedex

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NTN

Verpackung

AVAQ bestimmt und verpackt alle Geräte auf der Grundlage der Schutzanforderungen gegen elektrostatische Entladung (ESD) und Feuchtigkeitsempfindlichkeit (MSL)..