Diese Website verwendet Cookies. Durch die Nutzung dieser Website stimmen Sie der Verwendung von Cookies zu. Weitere Informationen finden Sie in unseren Datenschutzrichtlinie.

Die Bilder dienen nur als Referenz,

Siehe Technische Spezifikationen

TPIC6A259NE +BOM

8-bit addressable latch with 350mA/ch

Hersteller:

Texas Instruments, Inc
Herstellerteil #:

TPIC6A259NE
Datenblatt:

TPIC6A259NE Datenblatt (PDF)
Series:

TPIC
Logic Type:

D-Type, Addressable
Circuit:

1:8
Output Type:

DMOS
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an TPIC6A259NE

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

TPIC6A259NE Allgemeine Beschreibung

This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multi-functional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.

Four distinct modes of operation are selectable by controlling the clear (CLR\) and enable (G\) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS-transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G\ should be held high (inactive) while the address lines are changing. In the 8-line demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6A259 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body, surface-mount (DW) package. The TPIC6A259 is characterized for operation over the operating case temperature range of -40°C to 125°C.

Hauptmerkmale

Low r_DS(on) . . . 1 Typ
Output Short-Circuit Protection
Avalanche Energy . . . 75 mJ
Eight 350-mA DMOS Outputs
50-V Switching Capability
Four Distinct Function Modes
Low Power Consumption

Spezifikationen

Category	Integrated Circuits (ICs)LogicLatches	Series	TPIC
Logic Type	D-Type, Addressable	Circuit	1:8
Output Type	DMOS	Voltage - Supply	4.5V ~ 5.5V
Independent Circuits	1	Delay Time - Propagation	30ns
Current - Output High, Low	-	Operating Temperature	-40°C ~ 125°C
Mounting Type	Through Hole	Base Product Number	TPIC6A259

Servicerichtlinien und andere

After-Sales- und Abwicklungsbezogen

Zahlung

Bezahlverfahren

TT/Überweisung

Paypal

Western Union

Geldgramm

Für alternative Zahlungskanäle kontaktieren Sie uns bitte unter:

[email protected]

Versand & Verpackung

Versandart

Fedex

UPS

DHL

NTN

Verpackung

AVAQ bestimmt und verpackt alle Geräte auf der Grundlage der Schutzanforderungen gegen elektrostatische Entladung (ESD) und Feuchtigkeitsempfindlichkeit (MSL)..