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Siehe Technische Spezifikationen

TSB43AB23IPDTEP +BOM

1394 Interface IC Mil Enh OHCI PHY/ Link Layer Cntrlr

Hersteller:

Texas Instruments, Inc
Herstellerteil #:

TSB43AB23IPDTEP
Datenblatt:

TSB43AB23IPDTEP Datenblatt (PDF)
Programmable:

Not Verified
Protocol:

IEEE 1394
Function:

Physical Layer Controller
Interface:

PCI
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an TSB43AB23IPDTEP

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

TSB43AB23IPDTEP Allgemeine Beschreibung

IEEE 1394 Physical Layer Controller IEEE 1394-1995, 1394a-2000, OHCI, Firewire™, i.Link™ PCI Interface 128-TQFP (14x14)

Hauptmerkmale

Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial busand IEEE Std 1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
Compliant with Intel Mobile Power Guideline 2000
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down
Ultralow-power sleep mode
Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
Cable ports monitor line conditions for active connection to remote node
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Physical write posting of up to three outstanding transactions
PCI burst transfers and deep FIFOs to tolerate large host latency
PCI_CLKRUN\ protocol
External cycle timer control for customized synchronization
Extended resume signaling for compatibility with legacy DV components
PHY-link logic performs system initialization and arbitration functions
PHY-link encode and decode functions included for data-strobe bit level encoding
PHY-link incoming data resynchronized to local clock
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s
Node power class information signaling for system power management
Serial ROM interface supports 2-wire serial EEPROM devices
Two general-purpose I/Os
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features
Fabricated in advanced low-power CMOS process
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous transmit requests
Register access fail interrupt when the PHY SCLK is not active
PCI power-management D0, D1, D2, and D3 power states
Initial bandwidth available and initial channels available registers
PME\ support per 1394 Open Host Controller Interface Specification

Spezifikationen

Category	Integrated Circuits (ICs)InterfaceControllers	Series	-
Programmable	Not Verified	Protocol	IEEE 1394
Function	Physical Layer Controller	Interface	PCI
Standards	IEEE 1394-1995, 1394a-2000, OHCI, Firewire™, i.Link™	Voltage - Supply	3V ~ 3.6V
Current - Supply	-	Operating Temperature	-40°C ~ 85°C
Base Product Number	TSB43AB23

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