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XCR3032XL-10CSG48C +BOM

CPLD - Complex Programmable Logic Devices XCR3032XL-10CSG48C

Hersteller:

AMD Xilinx, Inc
Herstellerteil #:

XCR3032XL-10CSG48C
Datenblatt:

XCR3032XL-10CSG48C Datenblatt (PDF)
Series:

CoolRunner XPLA3
Programmable:

Not Verified
Programmable Type:

In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max:

9.1 ns
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an XCR3032XL-10CSG48C

XCR3032XL-10CSG48C Allgemeine Beschreibung

The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.

TotalCMOS Design Technique for Fast Zero Power

CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,both in process technology and design technique. TheseCPLDs employ a cascade of CMOS gates to implementtheir sum of products, instead of the traditional sense ampapproach. This CMOS gate implementation allows XilinxCPLDs to offer devices that are both high performance andlow power, breaking the paradigm that to have low power,you must have low performance.

Hauptmerkmale

Low power 3.3V 32 macrocell CPLD
4.5 ns pin-to-pin logic delays
System frequencies up to 213 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/Os)
Optimized for 3.3V systems
- Ultra-low power operation
- Typical Standby Current of 17 μA at 25°C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power (FZP) CMOS technology
- 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to the CoolRunner XPLA3 family data sheet (DS012) for architecture description

Spezifikationen

Category	Integrated Circuits (ICs)EmbeddedCPLDs (Complex Programmable Logic Devices)	Series	CoolRunner XPLA3
Programmable	Not Verified	Programmable Type	In System Programmable (min 1K program/erase cycles)
Delay Time tpd(1) Max	9.1 ns	Voltage Supply - Internal	3V ~ 3.6V
Number of Logic Elements/Blocks	2	Number of Macrocells	32
Number of Gates	750	Number of I/O	36
Operating Temperature	0°C ~ 70°C (TA)	Mounting Type	Surface Mount
Base Product Number	XCR3032

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