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Siehe Technische Spezifikationen

M4A5-192/96-10VNC +BOM

EE PLD, 10ns, 192-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

M4A5-192/96-10VNC
Datenblatt:

M4A5-192/96-10VNC Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

144
Reach Compliance Code:

compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an M4A5-192/96-10VNC

M4A5-192/96-10VNC Allgemeine Beschreibung

GENERAL DESCRIPTIONThe ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation.

Hauptmerkmale

High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature
— SpeedLockingTM performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	144	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Additional Feature	YES	Clock Frequency-Max	62.5 MHz
In-System Programmable	YES	JESD-30 Code	S-PQFP-G144
JESD-609 Code	e3	JTAG BST	YES
Length	20 mm	Moisture Sensitivity Level	3
Number of Dedicated Inputs	16	Number of I/O Lines	96
Number of Macro Cells	192	Number of Terminals	144
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	16 DEDICATED INPUTS, 96 I/O	Output Function	MACROCELL
Peak Reflow Temperature (Cel)	260	Programmable Logic Type	EE PLD
Propagation Delay	10 ns	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	5.25 V
Supply Voltage-Min	4.75 V	Supply Voltage-Nom	5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Finish	MATTE TIN
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	40
Width	20 mm

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