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P89LV51RC2FBC +BOM

Featuring 12 CLK ISP/IAP support

Hersteller:

NXP
Herstellerteil #:

P89LV51RC2FBC
Datenblatt:

P89LV51RC2FBC Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

44
ECCN Code:

3A991.A.2
HTS Code:

8542.31.00.01
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Fordern Sie kostenlose CAD-Modelle für an P89LV51RC2FBC

P89LV51RC2FBC Allgemeine Beschreibung

One of the standout features of the P89LV51RC2FBC is its support for various communication protocols like UART, SPI, and I2C. This flexibility makes it a breeze to connect and communicate with other devices, opening up a world of possibilities for your project. Plus, with built-in timers/counters and PWM outputs, this microcontroller is perfectly suited for applications that require precise timing control or analog device interfacing

Hauptmerkmale

Principal features
1 kB byte-erasable Flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
128-byte RAM data memory.
Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a port output upon timer overflow or to become a PWM output.)
23-bit system timer that can also be used as a Real-Time clock.
Two analog comparators (P89LPC902 and P89LPC903, single analog comparator on P89LPC901).
Enhanced UART with fractional baudrate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC903).
High-accuracy internal RC oscillator option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.
2.4 V to 3.6 V VDDoperating range with 5 V tolerant I/O pins (may be pulled up or driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1, 8, and 4.
Up to six I/O pins when using internal oscillator and reset options.
8-pin SO-8 package.
Additional features
A high performance 80C51 CPU provides instruction cycle times of 167 ns to 333 ns for all instructions except multiply and divide when executing at 12 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.
In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.
Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.
Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.
Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.
Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1µA (total Power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.
Configurable on-chip oscillator with frequency range options selected by user programmed Flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 12 MHz (P89LPC901).
Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values.
Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.
LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
Only power and ground connections are required to operate the P89LPC901/902/903 when internal reset option is selected.
Four interrupt priority levels.
Two (P89LPC901), three (P89LPC903), or five (P89LPC902) keypad interrupt inputs.
Second data pointer.
Schmitt trigger port inputs.
Emulation support.

Spezifikationen

Source Content uid	P89LV51RC2FBC	Part Life Cycle Code	Obsolete
Pin Count	44	Reach Compliance Code
ECCN Code	3A991.A.2	HTS Code	8542.31.00.01
Has ADC	NO	Address Bus Width	16
Bit Size	8	CPU Family	8051
Clock Frequency-Max	33 MHz	DAC Channels	NO
DMA Channels	NO	External Data Bus Width	8
JESD-30 Code	S-PQFP-G44	Length	10 mm
Moisture Sensitivity Level	3	Number of I/O Lines	32
Number of Terminals	44	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	PWM Channels	YES
Qualification Status	Not Qualified	RAM (bytes)	1024
ROM (words)	32768	ROM Programmability	FLASH
Seated Height-Max	1.2 mm	Speed	33 MHz
Supply Current-Max	30 mA	Supply Voltage-Max	3.6 V
Supply Voltage-Min	2.7 V	Supply Voltage-Nom	3 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	INDUSTRIAL	Terminal Form	GULL WING
Terminal Pitch	0.8 mm	Terminal Position	QUAD
Width	10 mm	uPs/uCs/Peripheral ICs Type	MICROCONTROLLER

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