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Siehe Technische Spezifikationen

W632GU6KB-12 +BOM

Exceptional reliability and efficiency for demanding applications, such as gaming, servers, and networking equipment

Hersteller:

WINBOND ELECTRONICS CORP
Herstellerteil #:

W632GU6KB-12
Datenblatt:

W632GU6KB-12 Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

96
Reach Compliance Code:

compliant
ECCN Code:

EAR99

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

W632GU6KB-12 Allgemeine Beschreibung

Elevate your computing experience with W632GU6KB-12, the ultimate choice for advanced memory needs. This DDR4 SDRAM chip packs a punch with its impressive 8GB capacity and 1Gx64 configuration, delivering unrivaled performance for your system. Running at an impressive frequency of 1200MHz, it ensures efficient and speedy data transfer, allowing you to work and play with ease. Whether you are a tech enthusiast or a professional in need of reliable memory solutions, W632GU6KB-12 is the perfect choice to enhance your computing experience. Say hello to faster loading times, smoother multitasking, and improved overall system performance with W632GU6KB-12

Hauptmerkmale

 Power Supply: VDD, VDDQ = 1.5V ± 0.075V
 Double Data Rate architecture: two data transfers per clock cycle
 Eight internal banks for concurrent operation
 8 bit prefetch architecture
 CAS Latency: 6, 7, 8, 9, 10, 11 and 13
 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On The-Fly (OTF)
 Programmable read burst ordering: interleaved or nibble sequential
 Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
 Edge-aligned with read data and center-aligned with write data
 DLL aligns DQ and DQS transitions with clock
 Differential clock inputs (CK and CK#)
 Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
 Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency
 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
 Auto-precharge operation for read and write bursts
 Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
 Precharged Power Down and Active Power Down

Spezifikationen

Part Life Cycle Code	Obsolete	Pin Count	96
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.36	Access Mode	MULTI BANK PAGE BURST
Access Time-Max	0.225 ns	Additional Feature	AUTO/SELF REFRESH
Clock Frequency-Max (fCLK)	800 MHz	I/O Type	COMMON
Interleaved Burst Length	8	JESD-30 Code	R-PBGA-B96
Length	13 mm	Memory Density	2147483648 bit
Memory IC Type	DDR3L DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	96	Number of Words	134217728 words
Number of Words Code	128000000	Operating Mode	SYNCHRONOUS
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	128MX16	Output Characteristics	3-STATE
Peak Reflow Temperature (Cel)	NOT SPECIFIED	Power Supplies	1.35 V
Qualification Status	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	8	Standby Current-Max	0.019 A
Supply Current-Max	0.38 mA	Supply Voltage-Max (Vsup)	1.45 V
Supply Voltage-Min (Vsup)	1.283 V	Supply Voltage-Nom (Vsup)	1.35 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	OTHER	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	9 mm

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