Bezahlverfahren
W972GG8KB25I +BOM
56MX8 0.4ns CMOS PBGA60
WBGA-60-
Hersteller:
WINBOND ELECTRONICS CORP
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Herstellerteil #:
W972GG8KB25I
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Datenblatt:
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Part Life Cycle Code:
Active
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Reach Compliance Code:
compliant
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ECCN Code:
EAR99
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HTS Code:
8542.32.00.36
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EDA/CAD Modelle:
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Verfügbarkeit: 9242 Stck
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W972GG8KB25I Allgemeine Beschreibung
What sets the W972GG8KB25I apart from other NAND flash memory chips is its exceptional speed capabilities. Operating at a maximum clock frequency of 50MHz, this chip enables rapid read and write operations, ideal for scenarios where quick data transfer is crucial. Its x8 I/O interface and 2KB page size further enhance its efficiency, while the organization of 64 blocks, each containing 64 pages, ensures optimal data management
Hauptmerkmale
- Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
- Double Data Rate architecture: two data transfers per clock cycle
- CAS Latency: 3, 4, 5, 6 and 7
- Burst Length: 4 and 8
- Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
- Edge-aligned with Read data and center-aligned with Write data
- DLL aligns DQ and DQS transitions with clock
- Differential clock inputs (CLK and CLK )
- Data masks (DM) for write data.
- Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
- Posted CAS programmable additive latency supported to make command and data bus efficiency
- Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
- Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
- Auto-precharge operation for read and write bursts
- Auto Refresh and Self Refresh modes
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = Read Latency - 1 (WL = RL - 1)
- Interface: SSTL_18
- Packaged in WBGA 60 Ball (11x11.5 mm2), using Lead free materials with RoHS compliant
Spezifikationen
Part Life Cycle Code | Active | Reach Compliance Code | compliant |
ECCN Code | EAR99 | HTS Code | 8542.32.00.36 |
Access Mode | MULTI BANK PAGE BURST | Access Time-Max | 0.4 ns |
Additional Feature | AUTO/SELF REFRESH | JESD-30 Code | R-PBGA-B60 |
Length | 12.5 mm | Memory Density | 2147483648 bit |
Memory IC Type | DDR2 DRAM | Memory Width | 8 |
Number of Functions | 1 | Number of Ports | 1 |
Number of Terminals | 60 | Number of Words | 268435456 words |
Number of Words Code | 256000000 | Operating Mode | SYNCHRONOUS |
Organization | 256MX8 | Peak Reflow Temperature (Cel) | NOT SPECIFIED |
Seated Height-Max | 1.2 mm | Self Refresh | YES |
Supply Voltage-Max (Vsup) | 1.9 V | Supply Voltage-Min (Vsup) | 1.7 V |
Supply Voltage-Nom (Vsup) | 1.8 V | Surface Mount | YES |
Technology | CMOS | Terminal Form | BALL |
Terminal Pitch | 0.8 mm | Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | Width | 8 mm |
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In Stock: 9.242
Minimum Order: 1
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