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Siehe Technische Spezifikationen

W9751G6IB-25 +BOM

ROHS compliant WBGA-84 memory component

Hersteller:

WINBOND ELECTRONICS CORP
Herstellerteil #:

W9751G6IB-25
Datenblatt:

W9751G6IB-25 Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

84
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an W9751G6IB-25

W9751G6IB-25 Allgemeine Beschreibung

With cutting-edge technology and a state-of-the-art design, the W9751G6IB-25 redefines memory performance with its 512MB capacity and lightning-fast 400MHz speed rating. The module's 64Mx8 configuration optimizes data processing efficiency, supported by a low 1.8V voltage for enhanced energy savings. Its 8 banks of 8Mx8 bits ensure seamless operation across various computing and networking applications, while the programmable CAS latency and refresh cycle time of 15.6μs guarantee smooth performance. Featuring a Serial Presence Detect EEPROM, the module effortlessly communicates vital information to the system BIOS, enabling optimal memory settings and system compatibility. Additionally, its RoHS compliance and wide temperature range of 0°C to 85°C make it a reliable choice for diverse operating environments

Hauptmerkmale

Power Supply: VDD, VDDQ = 1.8 V  0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant

Spezifikationen

Part Life Cycle Code	Obsolete	Pin Count	84
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.28	Access Mode	FOUR BANK PAGE BURST
Access Time-Max	0.4 ns	Additional Feature	AUTO/SELF REFRESH
Clock Frequency-Max (fCLK)	400 MHz	I/O Type	COMMON
Interleaved Burst Length	4,8	JESD-30 Code	R-PBGA-B84
Length	12.5 mm	Memory Density	536870912 bit
Memory IC Type	DDR2 DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	84	Number of Words	33554432 words
Number of Words Code	32000000	Operating Mode	SYNCHRONOUS
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	32MX16	Output Characteristics	3-STATE
Peak Reflow Temperature (Cel)	NOT SPECIFIED	Power Supplies	1.8 V
Qualification Status	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	4,8	Standby Current-Max	0.008 A
Supply Current-Max	0.3 mA	Supply Voltage-Max (Vsup)	1.9 V
Supply Voltage-Min (Vsup)	1.7 V	Supply Voltage-Nom (Vsup)	1.8 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	OTHER	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	10 mm

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