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Siehe Technische Spezifikationen

W9751G6KB25I +BOM

Industrial Temperature DRAM 512Mb DDR2-800, x16

Hersteller:

WINBOND ELECTRONICS CORP
Herstellerteil #:

W9751G6KB25I
Datenblatt:

W9751G6KB25I Datenblatt (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

84
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an W9751G6KB25I

W9751G6KB25I Allgemeine Beschreibung

The W9751G6KB25I is a cutting-edge DDR2 SDRAM chip meticulously engineered for demanding computational tasks. Boasting a substantial 1 Gb (128MB) capacity, a 1.8V power supply, and a clock frequency of 400 MHz, this chip sets the bar high for performance and efficiency. With its rapid data transfer rates and minimal power consumption, it is the go-to choice for desktops, laptops, and servers, delivering unparalleled reliability and speed

Hauptmerkmale

Power Supply: VDD, VDDQ = 1.8 V  0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant

Spezifikationen

Part Life Cycle Code	Obsolete	Pin Count	84
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.28	Access Mode	FOUR BANK PAGE BURST
Access Time-Max	0.4 ns	Additional Feature	AUTO/SELF REFRESH
Clock Frequency-Max (fCLK)	400 MHz	I/O Type	COMMON
Interleaved Burst Length	4,8	JESD-30 Code	R-PBGA-B84
JESD-609 Code	e1	Length	12.5 mm
Memory Density	536870912 bit	Memory IC Type	DDR2 DRAM
Memory Width	16	Number of Functions	1
Number of Ports	1	Number of Terminals	84
Number of Words	33554432 words	Number of Words Code	32000000
Operating Mode	SYNCHRONOUS	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	Organization	32MX16
Output Characteristics	3-STATE	Power Supplies	1.8 V
Qualification Status	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	4,8	Standby Current-Max	0.008 A
Supply Current-Max	0.2 mA	Supply Voltage-Max (Vsup)	1.9 V
Supply Voltage-Min (Vsup)	1.7 V	Supply Voltage-Nom (Vsup)	1.8 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	INDUSTRIAL	Terminal Finish	TIN SILVER COPPER
Terminal Form	BALL	Terminal Pitch	0.8 mm
Terminal Position	BOTTOM	Width	8 mm

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