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XQV100-4PQ240N +BOM

IC FPGA QPRO VIRTEX 240-PQFP

Hersteller:

XILINX
Herstellerteil #:

XQV100-4PQ240N
Datenblatt:

XQV100-4PQ240N Datenblatt (PDF)
ECCN (US):

EAR99
HTS:

8541.29.00.95
Automotive:

No
PPAP:

No
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an XQV100-4PQ240N

Hauptmerkmale

Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) Guaranteed over the full military temperature range (–55°C to +125°C) Ceramic and Plastic Packages Fast, high-density Field-Programmable Gate Arrays- Densities from 100K to 1M system gates- System performance up to 200 MHz- Hot-swappable for Compact PCI Multi-standard SelectI/O™ interfaces- 16 high-performance interface standards- Connects directly to ZBTRAM devices Built-in clock-management circuitry- Four dedicated delay-locked loops (DLLs) for advanced clock control- Four primary low-skew global clock distribution nets, plus 24 secondary global nets Hierarchical memory system- LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register- Configurable synchronous dual-ported 4K-bit RAMs- Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density- Dedicated carry logic for high-speed arithmetic- Dedicated multiplier support- Cascade chain for wide-input functions- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset- Internal 3-state bussing- IEEE 1149.1 boundary-scan logic- Die-temperature sensing device Supported by FPGA Foundation™ and Alliance Development Systems- Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager- Wide selection of PC and workstation platforms SRAM-based in-system configuration- Unlimited reprogrammability- Four programming modes
0.22 µm 5-layer metal process 100% factory tested Available to Standard Microcircuit Drawings- 5962-99572 for XQV300- 5962-99573 for XQV600- 5962-99574 for XQV1000

Spezifikationen

ECCN (US)	EAR99	Part Status	Unconfirmed
HTS	8541.29.00.95	Automotive	No
PPAP	No	Category	Power MOSFET
Configuration	Single	Channel Mode	Enhancement
Channel Type	N	Number of Elements per Chip	1
Maximum Drain Source Voltage (V)	600	Maximum Gate Source Voltage (V)	±30
Maximum Gate Threshold Voltage (V)	4	Maximum Continuous Drain Current (A)	33
Maximum Gate Source Leakage Current (nA)	100	Maximum IDSS (uA)	1
Maximum Drain Source Resistance (mOhm)	99@10V	Typical Gate Charge @ Vgs (nC)	100@10V
Typical Gate Charge @ 10V (nC)	100	Typical Input Capacitance @ Vds (pF)	3508@100V
Maximum Power Dissipation (mW)	278000	Typical Fall Time (ns)	54
Typical Rise Time (ns)	60	Typical Turn-Off Delay Time (ns)	99
Typical Turn-On Delay Time (ns)	28	Minimum Operating Temperature (°C)	-55
Maximum Operating Temperature (°C)	150	Mounting	Through Hole
PCB changed	3	Tab	Tab
Pin Count	3	Lead Shape	Through Hole

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