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Siehe Technische Spezifikationen

GAL16V8D-25QJN +BOM

GAL16V8D-25QJN is a versatile Programmable Logic Device that is suitable for a variety of applications

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

GAL16V8D-25QJN
Datenblatt:

GAL16V8D-25QJN Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Obsolete
Pin Count:

20
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an GAL16V8D-25QJN

GAL16V8D-25QJN Allgemeine Beschreibung

In summary, the GAL16V8D-25QJN is a state-of-the-art CPLD that combines high performance with user-friendly features. Its impressive speed, energy efficiency, and reprogrammability set it apart as a versatile solution for complex logic processing tasks. Whether you're a seasoned professional or just starting out in the field, this device offers the reliability and flexibility needed to bring your designs to life. Trust in the GAL16V8D-25QJN to power your next project with seamless efficiency and precision

Hauptmerkmale

HIGH PERFORMANCE E2CMOS®TECHNOLOGY
—3.5 ns Maximum Propagation Delay
—Fmax = 250 MHz
—3.0 ns Maximum from Clock Input to Data Output
—UltraMOS®
Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
—75mA Typ Icc on Low Power Device
—45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E2CELL TECHNOLOGY
—Reconfigurable Logic
—Reprogrammable Cells
—100% Tested/100% Yields
—High Speed Electrical Erasure (<100ms)
—20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
—Maximum Flexibility for Complex Logic Designs
—Programmable Output Polarity
—Also Emulates 20-pin PAL®
Devices with Full
Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
—100% Functional Testability
APPLICATIONS INCLUDE:
—DMA Control
—State Machine Control
—High Speed Graphics Processing
—Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
LEAD-FREE PACKAGE OPTIONS

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Obsolete
Pin Count	20	Reach Compliance Code
ECCN Code	EAR99	HTS Code	8542.39.00.01
Architecture	PAL-TYPE	Clock Frequency-Max	37 MHz
JESD-30 Code	S-PQCC-J20	JESD-609 Code	e3
Length	8.9662 mm	Moisture Sensitivity Level	1
Number of Dedicated Inputs	8	Number of I/O Lines	8
Number of Inputs	18	Number of Outputs	8
Number of Product Terms	64	Number of Terminals	20
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	8 DEDICATED INPUTS, 8 I/O	Output Function	MACROCELL
Peak Reflow Temperature (Cel)	250	Programmable Logic Type	EE PLD
Propagation Delay	25 ns	Qualification Status	Not Qualified
Seated Height-Max	4.572 mm	Supply Voltage-Max	5.25 V
Supply Voltage-Min	4.75 V	Supply Voltage-Nom	5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Finish	Matte Tin (Sn)
Terminal Form	J BEND	Terminal Pitch	1.27 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	40
Width	8.9662 mm

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