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DDR DRAM, 256MX16, CMOS, PBGA96, FBGA-96
TFBGAHersteller:
SK HYNIX INC
Herstellerteil #:
H5AN4G6NAFR-UHC
Datenblatt:
Part Life Cycle Code:
Active
Reach Compliance Code:
compliant
ECCN Code:
EAR99
HTS Code:
8542.32.00.36
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DescriptionThe H5AN4G4NAFR-xxC, H5AN4G8NAFR-xxC and H5AN4G6NAFR-xxC are a 4Gb CMOS Double Data RateIV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memorydensity and high bandwidth. SK hynix 4Gb DDR4 SDRAMs offer fully synchronous operations referencedto both rising and falling edges of the clock. While all addresses and control inputs are latched onthe rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs aresampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.FEATURES• VDD=VDDQ=1.2V +/- 0.06V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 9, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 • Programmable additive latency 0, CL-1, and CL-2 supported (x4/x8 only)• Programmable CAS Write latency (CWL) = 9, 10, 11, 12, 14, 16, 18• Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 16banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 μs at 0oC ~ 85 oC - 3.9 μs at 85oC ~ 95 oC• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)• Driver strength selected by MRS • Dynamic On Die Termination supported• Two Termination States such as RTT_PARK and RTT_NOM switchable by ODT pin• Asynchronous RESET pin supported • ZQ calibration supported• TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch • This product in compliance with the RoHS directive.• Internal Vref DQ level generation is available• Write CRC is supported at all speed grades• Maximum Power Saving Mode is supported• TCAR(Temperature Controlled Auto Refresh) mode is supported• LP ASR(Low Power Auto Self Refresh) mode is sup-ported• Fine Granularity Refresh is supported• Per DRAM Addressability is supported• Geardown Mode(1/2 rate, 1/4 rate) is supported• Programable Preamble for read and write is supported• Self Refresh Abort is supported• CA parity (Command/Address Parity) mode is sup-ported• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or differentbank group accesses are available• DBI(Data Bus Inversion) is supported(x8)
Part Life Cycle Code | Active | Reach Compliance Code | compliant |
ECCN Code | EAR99 | HTS Code | 8542.32.00.36 |
Access Mode | MULTI BANK PAGE BURST | Additional Feature | AUTO/SELF REFRESH |
JESD-30 Code | R-PBGA-B96 | Length | 13 mm |
Memory Density | 4294967296 bit | Memory IC Type | DDR4 DRAM |
Memory Width | 16 | Number of Functions | 1 |
Number of Ports | 1 | Number of Terminals | 96 |
Number of Words | 268435456 words | Number of Words Code | 256000000 |
Operating Mode | SYNCHRONOUS | Operating Temperature-Max | 85 °C |
Operating Temperature-Min | Organization | 256MX16 | |
Peak Reflow Temperature (Cel) | 260 | Seated Height-Max | 1.2 mm |
Self Refresh | YES | Supply Voltage-Max (Vsup) | 1.26 V |
Supply Voltage-Min (Vsup) | 1.14 V | Supply Voltage-Nom (Vsup) | 1.2 V |
Surface Mount | YES | Technology | CMOS |
Temperature Grade | OTHER | Terminal Form | BALL |
Terminal Pitch | 0.8 mm | Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | 20 | Width | 7.5 mm |
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