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LCMXO2-1200HC-6SG32I +BOM

LCMXO2-1200HC-6SG32I is an FPGA (Field Programmable Gate Array) from the MachXO2 series, featuring 1280 LUTs and supporting voltages of 2.5/3.3V

Hersteller:

LATTICE SEMICONDUCTOR CORP
Herstellerteil #:

LCMXO2-1200HC-6SG32I
Datenblatt:

LCMXO2-1200HC-6SG32I Datenblatt (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.39.00.01
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-1200HC-6SG32I

LCMXO2-1200HC-6SG32I Allgemeine Beschreibung

Lattice Semiconductor's LCMXO2-1200HC-6SG32I is a member of the XO2 family of FPGAs and is known for its high logic capacity, low power consumption, and impressive performance. Featuring 1200 Look-Up Tables for logic implementation and 32 I/O pins, this FPGA is designed to meet the demands of today's technology-driven world. Its Speed Grade designation and High Capacity status further highlight its suitability for various applications, from mobile devices to industrial automation systems

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

LATTICE SEMICONDUCTOR CORP Originalbestand

Spezifikationen

Part Life Cycle Code	Active	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Date Of Intro	2016-03-11	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-XQCC-N32	Length	5 mm
Moisture Sensitivity Level	1	Number of CLBs	160
Number of Inputs	21	Number of Logic Cells	1280
Number of Outputs	21	Number of Terminals	32
Operating Temperature-Max	100 °C	Operating Temperature-Min	-40 °C
Organization	160 CLBS	Packing Method	TRAY
Peak Reflow Temperature (Cel)	260	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Seated Height-Max	1 mm	Supply Voltage-Max	3.6 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Temperature Grade	INDUSTRIAL
Terminal Form	NO LEAD	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Width	5 mm

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