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LCMXO2-2000HC-4TG144C +BOM

LATTICE SEMICONDUCTOR - LCMXO2-2000HC-4TG144C - 144-pin TQFP packaging

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO2-2000HC-4TG144C
Datenblatt:

LCMXO2-2000HC-4TG144C Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

144
Reach Compliance Code:

compliant
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-2000HC-4TG144C

LCMXO2-2000HC-4TG144C Allgemeine Beschreibung

Positioned as an ideal solution for portable devices, consumer electronics, and industrial automation, the LCMXO2-2000HC-4TG144C strikes a balance between performance and cost-effectiveness. Its 144-pin TQFP package and support for various programming interfaces, including JTAG and SPI, make it a flexible choice for a wide range of applications. By offering reliable and efficient signal processing capabilities, this FPGA empowers designers to bring their innovative ideas to life

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	144	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY	Clock Frequency-Max	133 MHz
JESD-30 Code	S-PQFP-G144	JESD-609 Code	e3
Length	20 mm	Moisture Sensitivity Level	3
Number of Inputs	111	Number of Logic Cells	2112
Number of Outputs	111	Number of Terminals	144
Operating Temperature-Max	85 °C	Operating Temperature-Min
Packing Method	TRAY	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Temperature Grade	OTHER
Terminal Finish	Matte Tin (Sn)	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	20 mm

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