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Siehe Technische Spezifikationen

LCMXO2-256HC-4SG32C +BOM

The LCMXO2-256HC-4SG32C is a versatile 256 logic cell programmable logic device in a compact 32 QFN-32-EP(5x5) package."

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO2-256HC-4SG32C
Datenblatt:

LCMXO2-256HC-4SG32C Datenblatt (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.39.00.01
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-256HC-4SG32C

LCMXO2-256HC-4SG32C Allgemeine Beschreibung

The LCMXO2-256HC-4SG32C FPGA from Lattice Semiconductor is a high-performance device with low power consumption, making it an ideal choice for a wide range of applications. With 256 logic cells and a 4-speed grade, it operates at 32 MHz, delivering efficient processing power for consumer electronics, industrial automation, and communication systems. Its 1.2V core voltage and 90nm non-volatile process technology ensure reliable performance, and support for 3.3V and 2.5V I/O standards enhances its versatility. The FPGA also features embedded block RAM, distributed RAM, and PLLs for effective clock management. Its "HC" designation indicates its suitability for extended temperature ranges, making it a robust solution for use in harsh environments. In summary, the LCMXO2-256HC-4SG32C stands out as a powerful and efficient FPGA that offers high performance, low power consumption, and adaptability, making it a valuable choice for demanding applications

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Spezifikationen

Part Life Cycle Code	Active	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY	JESD-30 Code	S-XQCC-N32
Length	5 mm	Moisture Sensitivity Level	3
Number of CLBs	32	Number of Inputs	21
Number of Logic Cells	256	Number of Outputs	21
Number of Terminals	32	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	32 CLBS
Packing Method	TRAY	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	0.6 mm	Supply Voltage-Max (Vsup)	3.465 V
Supply Voltage-Min (Vsup)	2.375 V	Supply Voltage-Nom (Vsup)	2.5 V
Surface Mount	YES	Temperature Grade	OTHER
Terminal Form	NO LEAD	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Width	5 mm

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