Diese Website verwendet Cookies. Durch die Nutzung dieser Website stimmen Sie der Verwendung von Cookies zu. Weitere Informationen finden Sie in unseren Datenschutzrichtlinie.

Die Bilder dienen nur als Referenz,

Siehe Technische Spezifikationen

LCMXO2-256HC-4TG100I +BOM

Low power consumption

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO2-256HC-4TG100I
Datenblatt:

LCMXO2-256HC-4TG100I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-256HC-4TG100I

LCMXO2-256HC-4TG100I Allgemeine Beschreibung

The LCMXO2-256HC-4TG100I from Lattice Semiconductor is a powerful and flexible Field Programmable Gate Array (FPGA) that boasts 256 LUTs, 4,000 Logic Cells, and 4 global clock networks. With a maximum operating speed of 311 MHz and a 3.3V single-supply voltage, this FPGA delivers both high performance and power efficiency. It supports a range of I/O options, including LVCMOS, LVTTL, and LVDS standards, catering to diverse interface requirements. Housed in a compact 100-pin TQFP package, the LCMXO2-256HC-4TG100I is well-suited for space-constrained designs, making it an ideal choice for compact and portable applications. Additionally, its RoHS compliance underscores Lattice Semiconductor's commitment to environmental sustainability, making it a reliable and eco-friendly solution for FPGA implementations

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.39.00.01	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PQFP-G100	JESD-609 Code	e3
Length	14 mm	Moisture Sensitivity Level	3
Number of Inputs	55	Number of Logic Cells	256
Number of Outputs	55	Number of Terminals	100
Operating Temperature-Max	100 °C	Operating Temperature-Min	-40 °C
Packing Method	TRAY	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Terminal Finish	Matte Tin (Sn)
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	30
Width	14 mm

Servicerichtlinien und andere

After-Sales- und Abwicklungsbezogen

Zahlung

Bezahlverfahren

TT/Überweisung

Paypal

Western Union

Geldgramm

Für alternative Zahlungskanäle kontaktieren Sie uns bitte unter:

[email protected]

Versand & Verpackung

Versandart

Fedex

UPS

DHL

NTN

Verpackung

AVAQ bestimmt und verpackt alle Geräte auf der Grundlage der Schutzanforderungen gegen elektrostatische Entladung (ESD) und Feuchtigkeitsempfindlichkeit (MSL)..