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LCMXO2-4000HC-6MG132I +BOM

The LCMXO2-4000HC-6MG132I offers programmable functionality with a high pin count and compact footprint

Hersteller:

LATTICE SEMICONDUCTOR CORP
Herstellerteil #:

LCMXO2-4000HC-6MG132I
Datenblatt:

LCMXO2-4000HC-6MG132I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-4000HC-6MG132I

LCMXO2-4000HC-6MG132I Allgemeine Beschreibung

The Lattice Semiconductor LCMXO2-4000HC-6MG132I is a low-cost, low power Field-Programmable Gate Array (FPGA) that belongs to the Lattice XO2 family. It features 4000 Look-Up Tables (LUTs), 192 Kbits of embedded block RAM, and 80 user I/Os, operating at a speed grade of -6 with a maximum frequency of 144 MHz. This device is designed for applications requiring moderate logic density and a high I/O count, making it suitable for data processing, signal processing, and control tasks. It is programmed using the Lattice Diamond software tool, offering a user-friendly interface for design implementation and synthesis. With its cost-effective nature and low power consumption, the LCMXO2-4000HC-6MG132I is ideal for a wide range of applications in consumer electronics, industrial automation, communication systems, and more. Its compact size and high functionality make it a versatile choice for designers looking to implement custom logic solutions

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

LATTICE SEMICONDUCTOR CORP Originalbestand

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.39.00.01	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PBGA-B132	JESD-609 Code	e1
Length	8 mm	Moisture Sensitivity Level	3
Number of Inputs	104	Number of Logic Cells	4320
Number of Outputs	104	Number of Terminals	132
Operating Temperature-Max	100 °C	Operating Temperature-Min	-40 °C
Packing Method	TRAY	Peak Reflow Temperature (Cel)	250
Power Supplies	2.5/3.3 V	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	1.35 mm
Supply Voltage-Max	3.465 V	Supply Voltage-Min	2.375 V
Supply Voltage-Nom	2.5 V	Surface Mount	YES
Terminal Finish	Tin/Silver/Copper (Sn/Ag/Cu)	Terminal Form	BALL
Terminal Pitch	0.5 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	30	Width	8 mm

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