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LCMXO2-640UHC-4TG144I +BOM

LCMXO2-640UHC-4TG144I MACHX02 Series 640 LUTs 108 I/O 3.3 V -4 Speed IND Green FPGA TQFP-144

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO2-640UHC-4TG144I
Datenblatt:

LCMXO2-640UHC-4TG144I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-640UHC-4TG144I

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

LCMXO2-640UHC-4TG144I Allgemeine Beschreibung

Featuring an ultra-high density CMOS architecture, the LCMXO2-640UHC-4TG144I FPGA from Lattice Semiconductor offers an impressive capacity of 640 Look-Up Tables (LUTs) and 640 logic elements. This makes it an ideal solution for designers seeking greater logic integration in a compact footprint. The FPGA also comes equipped with 32Kbits of embedded memory and 64 I/O pins, enabling efficient data processing and seamless interfacing with external devices. With a maximum clock frequency of 120MHz and support for various standard I/O voltages, including 1.2V, 1.5V, 1.8V, and 2.5V, this FPGA is designed to deliver high performance while consuming minimal power. This combination of features makes the LCMXO2-640UHC-4TG144I well-suited for a wide range of battery-powered or portable electronic devices, offering a compelling balance of performance and efficiency

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.39.00.01	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PQFP-G144	JESD-609 Code	e3
Length	20 mm	Moisture Sensitivity Level	3
Number of Inputs	107	Number of Logic Cells	640
Number of Outputs	107	Number of Terminals	144
Operating Temperature-Max	100 °C	Operating Temperature-Min	-40 °C
Packing Method	TRAY	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Terminal Finish	Matte Tin (Sn)
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	30
Width	20 mm

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