Diese Website verwendet Cookies. Durch die Nutzung dieser Website stimmen Sie der Verwendung von Cookies zu. Weitere Informationen finden Sie in unseren Datenschutzrichtlinie.

LCMXO2-7000HC-4FTG256I 256-FTBGA (17x17)

Die Bilder dienen nur als Referenz,

Siehe Technische Spezifikationen

LCMXO2-7000HC-4FTG256I +BOM

Low-power CPLD in Lattice MachXO2 Family

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO2-7000HC-4FTG256I
Datenblatt:

LCMXO2-7000HC-4FTG256I Datenblatt (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

3A991.D
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO2-7000HC-4FTG256I

LCMXO2-7000HC-4FTG256I Allgemeine Beschreibung

Lattice Semiconductor brings you the LCMXO2-7000HC-4FTG256I, a powerful FPGA with 7000 logic cells and a high-speed design optimized for low-power applications. Featuring 256 pins for extensive connectivity and a durable 4FTG256I package type, this FPGA is built for seamless integration into your circuit board designs. Whether you're creating digital logic designs, signal processing algorithms, or other customizable hardware applications, the LCMXO2-7000HC-4FTG256I offers the versatility and performance you need. Its applications in industrial control systems, communication devices, and consumer electronics make it a reliable choice for a wide range of projects

Hauptmerkmale

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Spezifikationen

Pbfree Code	Yes	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	3A991.D
HTS Code	8542.39.00.01	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PBGA-B256	JESD-609 Code	e1
Length	17 mm	Moisture Sensitivity Level	3
Number of Inputs	206	Number of Logic Cells	6864
Number of Outputs	206	Number of Terminals	256
Operating Temperature-Max	100 °C	Operating Temperature-Min	-40 °C
Packing Method	TRAY	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.55 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Terminal Finish	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	30
Width	17 mm

Servicerichtlinien und andere

After-Sales- und Abwicklungsbezogen

Zahlung

Bezahlverfahren

TT/Überweisung

Paypal

Western Union

Geldgramm

Für alternative Zahlungskanäle kontaktieren Sie uns bitte unter:

[email protected]

Versand & Verpackung

Versandart

Fedex

UPS

DHL

NTN

Verpackung

AVAQ bestimmt und verpackt alle Geräte auf der Grundlage der Schutzanforderungen gegen elektrostatische Entladung (ESD) und Feuchtigkeitsempfindlichkeit (MSL)..