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LCMXO640C-3FN256C +BOM

FPGA - Field Programmable Gate Array 640 LUTS 159 I/O

LCMXO640C-3FN256C Allgemeine Beschreibung

The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.

The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology andcareful design will provide the high pin-to-pin performance also associated with CPLDs.

The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXOfamily of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER toolsuse the synthesis tool output along with the constraints from its floor planning tools to place and route the design inthe MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the designfor timing verification.

Lattice Semiconductor Corp Inventar
Lattice Semiconductor Corp Originalbestand
Lattice Semiconductor Corp Inventar

Spezifikationen

Mount Surface Mount Number of Pins 256
Max Frequency 500 MHz Max Operating Temperature 85 °C
Max Supply Voltage 3.465 V Memory Type SRAM
Min Operating Temperature 0 °C Min Supply Voltage 1.71 V
Nominal Supply Current 17 mA Number of I/Os 159
Number of Logic Blocks (LABs) 80 Number of Logic Elements/Cells 640
Number of Macrocells 320 Number of Programmable I/O 144
Operating Supply Current 17 mA Operating Supply Voltage 3.3 V
Propagation Delay 4.9 ns RAM Size 0 B

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