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LCMXO640C-3FTN256C +BOM

MachXO series device operating at 1.8V, 2.5V, or 3.3V

Hersteller:

Lattice Semiconductor Corporation
Herstellerteil #:

LCMXO640C-3FTN256C
Datenblatt:

LCMXO640C-3FTN256C Datenblatt (PDF)
Programmabe:

Not Verified
Number Of LABs/CLBs:

80
Number Of Logic Elements/Cells:

640
Number Of I/O:

159
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an LCMXO640C-3FTN256C

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

LCMXO640C-3FTN256C Allgemeine Beschreibung

The LCMXO640C-3FTN256C from Lattice Semiconductor is a versatile FPGA IC designed for high-volume applications in the consumer, communication, and industrial markets. With 640 LUTs, 32Kbits of embedded SRAM, and 48 user I/Os, this low-cost, low-power device offers a range of features to support complex system designs. It operates at a speed grade of 3 and comes in a 256-pin fine-pitch BGA package, making it suitable for demanding applications where both performance and compactness are essential. The non-volatile configuration memory ensures that the FPGA can retain its configuration even when powered off, simplifying the overall system design by eliminating the need for external configuration memory. Additionally, the LCMXO640C-3FTN256C supports advanced features such as Clock Conditioning Circuits (CCC), Phase-Locked Loops (PLLs), and built-in JTAG programming, providing flexibility and ease of use in device configuration. As such, the LCMXO640C-3FTN256C is an ideal choice for designers looking to achieve high performance and functionality in a cost-effective and power-efficient manner

Hauptmerkmale

Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single chip, no external configuration memory
required
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
Sleep Mode
Allows up to 100x static current reduction
TransFR™ Reconfiguration (TFR)
In-field logic update while system operates
High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
Flexible I/O Buffer
Programmable sysIO™ buffer supports wide
range of interfaces:
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK™ PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming

Spezifikationen

Programmabe	Not Verified	Number of LABs/CLBs	80
Number of Logic Elements/Cells	640	Total RAM Bits	-
Number of I/O	159	Number of Gates	-
Voltage - Supply	1.71V ~ 3.465V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)

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