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MB91F223 +BOM

32-bitMicrocontroller

Hersteller:

FUJITSU
Herstellerteil #:

MB91F223
Datenblatt:

MB91F223 Datenblatt (PDF)
Paket/Koffer:

QFP
EDA/CAD Modelle:

Fordern Sie kostenlose CAD-Modelle für an MB91F223

MB91F223 Allgemeine Beschreibung

■ OVERVIEWMB91220/S series is a line of single-chip microcontrollers based on a 32-bit high-performance RISC CPU and integrating a variety of I/O resources for embedded control applications.The MB91220/S series is designed to be best suited for embedded applications which require high-speed and high-performance processing power in the CPU, such as DVD players, printers, TV sets, and the PDP control.The MB91220/S series is a line of CPUs in the FR60Lite implemented by FR* family.■ FEATURES• FR60Lite CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier-PLL clock multiplier system) • 16-bit fixed-length instructions (basic instructions) • Instruction execution speed : 1 instruction per cycle • Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc. • Instructions supported by C language : Function entry/exit instructions, multiple-register load/store instructions. • Register interlock function : Easier assembler coding enabled • Built-in multiplier supported at the instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles • Interrupt (PC/PS save) : 6 cycles (16 priority levels) • Harvard architecture allowing program access and data access to be executed simultaneously. • Instruction set compatible with FR family • Internal Peripheral Functions • Internal ROM size & ROM type Flash Memory : 512 Kbytes (MB91F223/S) • Internal RAM size : 16 Kbytes (MB91F223/S) / 64 Kbytes (MB91V220) • General-purpose ports : up to 120 ports (including 4 input-only ports) • 8/10-bit A/D converter (Sequential comparison type) 8/10-bit resolution : 24 channels Conversion time : 3 µs (16/32 MHz) Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is achieved. 32 MHz : Source oscillation (4 MHz) with ×8 multiplier, divided by 1 16 MHz : Source oscillation with ×8 multiplier, divided by 2 • D/A converter (R-2R type) 8-bit resolution : 2 channels • External interrupt : 8 channels • Bit search module (for REALOS) • LIN-UART (full duplex double buffer type) : 4 channels Synchronous/asynchronous clock operations selectable Sync-break detection Dedicated built-in baud-rate generator • I2C Bus interface* : 2 channels • Stepping motor controller (SMC) : 4 channels 10-bit PWM with 4 high-current outputs for each channel • 8/16-bit PPG timer : 16 channels • 16-bit reload timer : 3 channels • 16-bit free-run timer : 2 channels (ICU/OCU linkage) • 16-bit pulse width counter : 1 channel • Input capture : 4 channels (free-run timers ch.0 and ch.1). ch.0 linked to PWC • Output compare : 2 channels (free-run timer ch.0 ) • LCD controller : SEG0 to SEG31/COM0 to COM3 (shared with port) • 16-bit timebase/watch dog timer • Sound generator : 3 channels • Real-time clock • 32 kHz sub clock (not supported in devices with an S suffix in the part number) • C-CAN : 2 channels • Low power consumption modes : sleep mode, stop mode, watch mode • Package : LQFP-144 (FPT-144P-M08) • CMOS technology : 0.35 µm • Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used))

Hauptmerkmale

FR60Lite CPU
32-bit RISC, load/store architecture, 5-stage pipeline
Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier-PLL clock multiplier system)
16-bit fixed-length instructions (basic instructions)
Instruction execution speed : 1 instruction per cycle
Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc.
Instructions supported by C language : Function entry/exit instructions, multiple-register load/store instructions.
Register interlock function : Easier assembler coding enabled
Built-in multiplier supported at the instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt (PC/PS save) : 6 cycles (16 priority levels)
Harvard architecture allowing program access and data access to be executed simultaneously.
Instruction set compatible with FR family
Internal Peripheral Functions
Internal ROM size & ROM type
Flash Memory : 512 Kbytes (MB91F223/S)
Internal RAM size : 16 Kbytes (MB91F223/S) / 64 Kbytes (MB91V220)
General-purpose ports : up to 120 ports (including 4 input-only ports)
8/10-bit A/D converter (Sequential comparison type)
8/10-bit resolution : 24 channels
Conversion time : 3 µs (16/32 MHz)
Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is achieved.
32 MHz : Source oscillation (4 MHz) with ×8 multiplier, divided by 1
16 MHz : Source oscillation with ×8 multiplier, divided by 2
D/A converter (R-2R type)
8-bit resolution : 2 channels
External interrupt : 8 channels
Bit search module (for REALOS)
LIN-UART (full duplex double buffer type) : 4 channels
Synchronous/asynchronous clock operations selectable
Sync-break detection
Dedicated built-in baud-rate generator
I2C Bus interface : 2 channels
Stepping motor controller (SMC) : 4 channels
10-bit PWM with 4 high-current outputs for each channel
8/16-bit PPG timer : 16 channels
16-bit reload timer : 3 channels
16-bit free-run timer : 2 channels (ICU/OCU linkage)
16-bit pulse width counter : 1 channel
Input capture : 4 channels (free-run timers ch.0 and ch.1). ch.0 linked to PWC
Output compare : 2 channels (free-run timer ch.0 )
LCD controller : SEG0 to SEG31/COM0 to COM3 (shared with port)
16-bit timebase/watch dog timer

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