Bezahlverfahren
TDA8007BHL/C4 +BOM
NXP Semiconductors TDA8007BHL/LQFP48//C4/REEL 13 Q1/T1 *STANDARD MAR
TQFP48-
Hersteller:
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Herstellerteil #:
TDA8007BHL/C4
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Datenblatt:
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Paket/Koffer:
TQFP48
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Produktart:
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RoHS:
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Lebenszyklus:
Active
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TDA8007BHL/C4 Allgemeine Beschreibung
The TDA8007BHL is a cost-effective card interface for dual smart card readers. Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11, EMV4.2 and EMV 2000. It is addressed on a non-multiplexed 8-bit databus, by means of address registers AD0, AD1, AD2 and AD3. TDA8007BHL/C3 can be also addressed through a multiplexed access. The integrated ISO UART and the time-out counters allow easy use even at high baud rates with no real time constraints. Due to its chip select, external input/output and interrupt features, it greatly simplifies the realization of a reader of any number of cards. It gives the cards and the reader a very high level of security, due to its special hardware against ESD, short-circuiting, power failure, etc. The integrated step-up converter allows operation within a supply voltage range of 2.7 V to 6 V.
TDA8007BHL/C4 supports only non multiplex access and TDA8007BHL/C3 support both non multiplexed and multiplexed access.
Hauptmerkmale
- Control and communication through an 8-bit parallel interface, compatible with non-multiplexed memory access, TDA8007BHL/C3 can be also addressed through a multiplexed memory access
- Specific ISO UART with parallel access input/output for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0 and extra guard time register
- FIFO for 1 to 8 characters in reception mode
- Parity error counter in reception mode and in transmission mode with automatic re-transmission
- Dual VCC generation: 5 V ± 5 %, 65 mA (max.); 3 V ± 8 %, 50 mA (max.) or 1.8 V ± 10 %, 30 mA (max.); with controlled rise and fall times
- Dual cards clock generation (up to 10 MHz), with three times synchronous frequency doubling (fXTAL, 1/2fXTAL, 1/4fXTAL and 1/8fXTAL)
- Cards clock stop (at high or low level) or 1.25 MHz (from internal oscillator) for cards Power-down mode
- Automatic activation and deactivation sequence through an independent sequencer
- Supports the asynchronous protocols T = 0 and T = 1 in accordance with: ISO 7816 and EMV4.2
- Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times processing
- Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT): 22 in T = 1 and 16 in T = 0
- Minimum delay between two characters in reception mode:
- in Protocol T = 0: 11.8 ETU
- in Protocol T = 1: 10.8 ETU
- Supports synchronous cards
- Current limitations in the event of short-circuit (pins I/O1, I/O2, VCC1, VCC2, RST1 and RST2)
- Special circuitry for killing spikes during power-on/power-off
- Supply supervisor for power-on/power-off reset
- Step-up converter (supply voltage from 2.7 V to 6 V), doubler, tripler or follower according to VCC and VDD
- Additional input/output pin allowing use of the ISO UART for another analog interface (pin I/OAUX)
- Additional interrupt pin allowing detection of level toggling on an external signal (pin INTAUX)
- Fast and efficient swapping between the three cards due to separate buffering of parameters for each card
- Chip select input allowing use of several devices in parallel and memory space paging
- Enhanced ESD protections on card side (except C4x, C8x): 6 kV (min.)
- Software library for easy integration within the application
- Power-down mode for reducing current consumption when no activity.
- Target Applications
- Multiple smart card readers for multiprocessor applications (EMV banking, digital payTV and access control, etc.).
Spezifikationen
Product Category: | NXP Semiconductors |
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